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Low Power, 24-Bit Sigma-Delta ADC with In-
Amp and Embedded Reference (6 Channel)
Preliminary Technical Data
AD7794
REV.PrE 6/04.
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
2004 Analog Devices, Inc. All rights reserved.
FEATURES
Six Differential Analog Inputs
Low Noise Programmable Gain Instrumentation-Amp
RMS noise: 80 nV (Gain = 64)
Bandgap Reference with 5 ppm/ C Drift typ
Power
Supply: 2.7 V to 5.25 V operation
Normal: 400 A typ
Power-down: 1 A max
Update Rate: 4 Hz to 500 Hz
Simultaneous 50 Hz/60 Hz Rejection
Internal Clock Oscillator
Reference Detect
Programmable Current Sources (10 A/200 A/1 mA)
On-Chip Bias Voltage Generator
100 nA Burnout Currents
Low Side Power Switch
Independent Interface Power Supply
24-Lead TSSOP Package
INTERFACE
3-wire serial
SPI, QSPITM, MICROWIRETM, and DSP compatible
Schmitt trigger on SCLK
APPLICATIONS
Temperature measurement
Pressure measurement
Weigh scales
GENERAL DESCRIPTION
The AD7794 is a low power, complete analog front end for
low frequency measurement applications. It contains a low
noise 24-bit - ADC with six differential inputs. The on-chip
low noise instrumentation amplifier means that signals of small
amplitude can be interfaced directly to the ADC.
The device contains a precision low noise, low drift internal
reference for absolute measurements. An external reference can
also be used if ratiometric measurements are required. Other
on-chip features include programmable excitation current
sources and a bias voltage generator for temperature applica-
tions along with 100 nA burnout currents. For pressure and
weighscale applications, a low-side power switch is available to
power down the bridge between conversions to minimize the
power consumption of the system. The device can be operated
with the internal clock or, alternatively, an external clock can be
used if synchronizing several devices. The output data rate
from the part is software programmable and can be varied from
4 Hz to 500 Hz.
The part operates with a power supply from 2.7 V to 5.25 V. It
consumes a current of 450 uA maximum and is housed in a 24-
lead TSSOP package.
FUNCTIONAL BLOCK DIAGRAM
AD7794
SERIAL
INTERFACE
AND
CONTROL
LOGIC
INTERNAL
CLOCK
CLK
SIGMA DELTA
ADC
AIN1(+)
AIN1(-)
AIN5(+)/IOUT2
AIN5(-)/IOUT1
MUX
IN-AMP
REFIN1(+)
REFIN1(-)
BANDGAP
REFERENCE
GND
VDD
GND
VDD
PSW
REFERENCE
DETECT
AIN2(+)
AIN2(-)
AIN6(+)/P1
AIN6(-)/P2
AIN3(+)
AIN3(-)
AIN4(+)/REFIN2(+)
AIN4(-)/REFIN2(-)
VBIAS
GND
GND
AVDD
DOUT/RDY
DIN
SCLK
CS
DVDD
TEMP
SENSOR
AD7794
Preliminary Technical Data
REV.PrE 6/04 | Page 2
TABLE OF CONTENTS
AD7794--Specifications.................................................................. 3
Timing Characteristics
,
.................................................................... 9
Absolute Maximum Ratings.......................................................... 11
ESD Caution................................................................................ 11
Pin Configuration and Function Descriptions........................... 12
Typical Performance Characteristics ........................................... 14
On-chip Registers ........................................................................... 15
Communications Register (RS2, RS1, RS0 = 0, 0, 0) .............. 15
Status Register (RS2, RS1, RS0 = 0, 0, 0; Power-on/Reset =
0x88)............................................................................................. 16
Mode Register (RS2, RS1, RS0 = 0, 0, 1; Power-on/Reset =
0x000A)........................................................................................ 16
Configuration Register (rs2, RS1, RS0 = 0, 1, 0; Power-
on/Reset = 0x0710) .................................................................... 18
Data Register (RS2, RS1, RS0 = 0, 1, 1; Power-on/Reset =
0x000000) .................................................................................... 20
ID Register (RS2, RS1, RS0 = 1, 0, 0; Power-on/Reset = 0xxF)
....................................................................................................... 20
IO Register (RS2, RS1, RS0 = 1, 0, 1; Power-on/Reset = 0x00)
....................................................................................................... 20
OFFSET Register (RS2, RS1, RS0 = 1, 1, 0; Power-on/Reset =
0x800000) .................................................................................... 21
FULL-SCALE Register (RS2, RS1, RS0 = 1, 1, 1; Power-
on/Reset = 0x5xxxx5) ................................................................ 21
ADC Circuit Information.............................................................. 22
Overview ..................................................................................... 22
Noise Performance ..................................................................... 22
Digital Interface .......................................................................... 23
Single Conversion Mode ....................................................... 24
Continuous Conversion Mode............................................. 24
Continuous Read Mode ........................................................ 25
Circuit Description......................................................................... 26
Analog Input Channel ............................................................... 26
Bipolar/Unipolar Configuration .............................................. 26
Data Output Coding .................................................................. 26
Reference ..................................................................................... 26
V
DD
Monitor ................................................................................ 27
Grounding and Layout .............................................................. 27
Outline Dimensions ....................................................................... 29
Ordering Guide .......................................................................... 29
REVISION HISTORY
REV.PrE, June 2004: Initial Version
Preliminary Technical Data
AD7794
REV.PrE 6/04 | Page 3
AD7794--SPECIFICATIONS
1
Table 1. (AV
DD
= 2.7 V to 5.25 V; DV
DD
= 2.7 V to 5.25 V; GND = 0 V; all specifications T
MIN
to T
MAX
, unless otherwise noted.)
Parameter AD7794B
Unit
Test
Conditions/Comments
AD7794 (CHOP ENABLED)
Output Update Rate
4
Hz min nom
Settling Time = 2/Output Update Rate
500
Hz max nom
No Missing Codes
2
24
Bits
min
f
ADC
125 Hz
Resolution (pk pk)
16
Bits p-p
Gain = 128, 16.6 Hz Update Rate, V
REF
= 2.5 V
19
Bits p-p
Gain = 1, 16.6 Hz Update Rate, V
REF
= 2.5 V
Output Noise and Update Rates
See Tables in ADC
Description
Integral Nonlinearity
15
ppm of FSR max
3.5 ppm typ. Gain = 1 to 32
25
ppm of FSR max
5 ppm typ, Gain = 64 or 128
Offset Error
3
3
V
typ
Offset Error Drift vs. Temperature
4
10
nV/C
typ
Full-Scale Error
3, 5
10
V
typ
Gain Drift vs. Temperature
4
0.5
ppm/C typ
Gain = 1 or 2
3
ppm/C typ
Gain = 4 to 128
Power Supply Rejection
90
dB min
100 dB typ, AIN = FS/2
ANALOG INPUTS
Differential Input Voltage Ranges
REFIN/Gain
V nom
REFIN = REFIN(+) REFIN() or Internal Reference,
Gain = 1 to 128
Absolute AIN Voltage Limits
2
Unbuffered Mode
GND 30 mV
V min
Gain = 1 or 2
AV
DD
+ 30 mV
V max
Buffered Mode
GND + 100 mV
V min
Gain = 1 or 2
AV
DD
100 mV
V max
In-Amp Enabled
GND + 300 mV
V min
Gain = 4 to 128
AV
DD
1.1
V max
Common Mode Voltage
0.5
V min
Gain = 4 to 128
Analog Input Current
Buffered Mode or In-Amp Enabled
Average Input Current
2
200
pA max
Average Input Current Drift
2
pA/C typ
Unbuffered Mode
Gain = 1 or 2
Average Input Current
400
nA/V typ
Input current varies with input voltage.
Average Input Current Drift
50
pA/V/C typ
1
nA max
AIN6(+) / AIN6(-)
Normal Mode Rejection
2
Internal Clock
@ 50 Hz, 60 Hz
70
dB min
80 dB typ, 50 1 Hz, 60 1 Hz, FS[3:0] = 1010
6
@ 50 Hz
84
dB min
90 dB typ, 50 1 Hz, FS[3:0] = 1001
6
@ 60 Hz
90
dB min
100 dB typ, 60 1 Hz, FS[3:0] = 1000
6
External Clock
@ 50 Hz, 60 Hz
80
dB min
90 dB typ, 50 1 Hz, 60 1 Hz, FS[3:0] = 1010
6
@ 50 Hz
94
dB min
100 dB typ, 50 1 Hz, FS[3:0] = 1001
6
@ 60 Hz
Common Mode Rejection
90
dB min
100 dB typ, 60 1 Hz, FS[3:0] = 1000
6
AIN = +FS/2
@DC
90
dB min
FS[3:0] = 1010
6
@ 50 Hz, 60 Hz
2
100
dB min
50 1 Hz, 60 1 Hz, FS[3:0] = 1010
6
@ 50 Hz, 60 Hz
2
100
dB
min
50 1 Hz (FS[3:0] = 1001
6
), 60 1 Hz (FS[3:0] =
1000
6
)
AD7794
Preliminary Technical Data
REV.PrE 6/04 | Page 4
Parameter AD7794B
Unit
Test
Conditions/Comments
REFERENCE INPUT
Internal Reference Initial Accuracy
1.17 0.01%
V min/max
Internal Reference Drift
5
ppm/C typ
15
ppm/C
max
Internal Reference Noise
2
V RMS
Gain = 1, Update Rate = 16.6 Hz. Includes ADC
Noise.
External REFIN Voltage
2.5
V nom
REFIN = REFIN(+) REFIN()
Reference Voltage Range
2
0.1 V
min
AV
DD
V
max
Absolute REFIN Voltage Limits
2
GND 30 mV
V min
AV
DD
+ 30 mV
V max
Average Reference Input Current
400
nA/V typ
Average Reference Input Current Drift
0.03
nA/V/C typ
Normal Mode Rejection
2
Same as for Analog
Inputs
Common Mode Rejection
Same as for Analog
Inputs
Reference Detect Levels
0.3
V min
NOXREF Bit Inactive if VREF < 0.3 V
0.65
V max
NOXREF Bit Active if VREF > 0.65 V
Preliminary Technical Data
AD7794
REV.PrE 6/04 | Page 5
Parameter AD7794B
Unit
Test
Conditions/Comments
AD7794 (CHOP DISABLED)
Output Update Rate
4
Hz min nom
Settling Time = 1/Output Update Rate
500
Hz max nom
No Missing Codes
2
24
Bits
min
f
ADC
125 Hz
Resolution 15.5
Bits
p-p
Gain
= 128, 16.6 Hz Update Rate, V
REF
= 2.5 V
18.5
Bits p-p
Gain = 1, 16.6 Hz Update Rate, V
REF
= 2.5 V
Output Noise and Update Rates
See Tables in ADC
Description
Integral Nonlinearity
15
ppm of FSR max
3.5 ppm of FSR typ. Gain = 1 to 32
25
ppm of FSR max
5 ppm of FSR typ, Gain = 64 or 128
Offset Error
3
200/Gain
V
typ
Without Calibration
Offset Error Drift vs. Temperature
4
200/Gain
nV/C
typ
Full-Scale Error
3, 5
10
V
typ
Gain Drift vs. Temperature
4
0.5
ppm/C typ
Gain = 1 or 2
3
ppm/C typ
Gain = 4 to 128
Power Supply Rejection
80
dB min
100 dB typ, AIN = FS/2
ANALOG INPUTS
Differential Input Voltage Ranges
REFIN/Gain
V nom
REFIN = REFIN(+) REFIN() or Internal Reference,
Gain = 1 to 128
Absolute AIN Voltage Limits
2
Unbuffered Mode
GND 30 mV
V min
Gain = 1 or 2
AV
DD
+ 30 mV
V max
Buffered Mode
GND + 100 mV
V min
Gain = 1 or 2
AV
DD
100 mV
V max
In-Amp Enabled
GND + 100 mV
V min
Gain = 4 to 128
AV
DD
1.1
V max
Common Mode Voltage
0.5
V min
Gain = 4 to 128
Analog Input Current
Buffered Mode or In-Amp Enabled
Average Input Current
2
200
pA max
Average Input Current Drift
2
pA/C typ
Unbuffered Mode
Gain = 1 or 2
Average Input Current
400
nA/V typ
Input current varies with input voltage.
Average Input Current Drift
50
pA/V/C typ
1
nA max
AIN6(+) / AIN6(-)
Normal Mode Rejection
2
Internal Clock
@ 50 Hz, 60 Hz
60
dB min
70 dB typ, 50 1 Hz, 60 1 Hz, FS[3:0] = 1010
6
@ 50 Hz
80
dB min
90 dB typ, 50 1 Hz, FS[3:0] = 1001
6
@ 60 Hz
90
dB min
100 dB typ, 60 1 Hz, FS[3:0] = 1000
6
External Clock
@ 50 Hz, 60 Hz
60
dB min
70 dB typ, 50 1 Hz, 60 1 Hz, FS[3:0] = 1010
6
@ 50 Hz
94
dB min
100 dB typ, 50 1 Hz, FS[3:0] = 1001
6
@ 60 Hz
90
dB min
100 dB typ, 60 1 Hz, FS[3:0] = 1000
6
Common Mode Rejection
AIN = +FS/2
@DC
80
dB min
FS[3:0] = 1010
6
@ 50 Hz, 60 Hz
2
80
dB min
50 1 Hz, 60 1 Hz, FS[3:0] = 1010
6
@ 50 Hz, 60 Hz
2
80
dB
min
50 1 Hz (FS[3:0] = 1001
6
), 60 1 Hz (FS[3:0] =
1000
6
)
REFERENCE INPUT
Internal Reference Initial Accuracy
1.17 0.01%
V min/max
Internal Reference Drift
5
ppm/C typ
15
ppm/C
max
AD7794
Preliminary Technical Data
REV.PrE 6/04 | Page 6
Parameter AD7794B
Unit
Test
Conditions/Comments
Internal Reference Noise
2
V RMS
Gain = 1, Update Rate = 16.6 Hz. Includes ADC
Noise.
External REFIN Voltage
2.5
V nom
REFIN = REFIN(+) REFIN()
Reference Voltage Range
2
0.1 V
min
V
DD
V
max
Absolute REFIN Voltage Limits
2
GND 30 mV
V min
AV
DD
+ 30 mV
V max
Average Reference Input Current
400
nA/V typ
Average Reference Input Current Drift
0.03
nA/V/C typ
Normal Mode Rejection
2
Same as for Analog
Inputs
Common Mode Rejection
Same as for Analog
Inputs
Reference Detect Levels
0.3
V min
NOXREF Bit Inactive if VREF < 0.3 V
0.65
V max
NOXREF Bit Active if VREF > 0.65 V
Preliminary Technical Data
AD7794
REV.PrE 6/04 | Page 7
Parameter AD7794B
Unit
Test
Conditions/Comments
EXCITATION CURRENT SOURCES (IEXC1 and IEXC2)
Output Current
10/200/1000
A nom
Initial Tolerance at 25C
5
% typ
Drift 200
ppm/C
typ
Initial Current Matching at 25C
1
% typ
Matching between IEXC1 and EXC2. V
OUT
= 0 V
Drift Matching
20
ppm/C typ
Line Regulation (V
DD
) 2.1
ppm/V
max
AV
DD
= 5 V 5%. Typically 1.25 ppm/V
Load Regulation
0.3
ppm/V typ
Output Compliance
AV
DD
0.6
V max
Current Sources Programmed to 10 A or 200 A
AV
DD
1
V max
Current Sources Programmed to 1 mA
GND 30 mV
V min
BIAS VOLTAGE GENERATOR
V
BIAS
AV
DD
/2 V
nom
V
BIAS
Generator Start-Up Time
TBD
ms/nF typ
Dependent on the Capacitance connected to AIN
TEMPERATURE SENSOR
Accuracy TBD
C
typ
LOW SIDE POWER SWITCH
R
ON
5
max
AV
DD
= 5 V
7
max
AV
DD
= 3 V
Allowable Current
20
mA max
Continuous Current
DIGITAL OUTPUTS (P1 & P2)
V
OH
, Output High Voltage
2
AV
DD
0.6
V min
AV
DD
= 3 V, I
SOURCE
= 100 A
V
OL
, Output Low Voltage
2
0.4
V
max
AV
DD
= 3 V, I
SINK
= 100 A
V
OH
, Output High Voltage
2
4
V
min
AV
DD
= 5 V, I
SOURCE
= 200 A
V
OL
, Output Low Voltage
2
0.4
V
max
AV
DD
= 5 V, I
SINK
= 800 A
Floating-State Leakage Current
1
A max
Floating-State Output Capacitance 10
pF
typ
INTERNAL/EXTERNAL CLOCK
Internal Clock
Fequency
64 2%
64 2%
Duty Cycle
50:50
50:50
Drift 0.01
0.01
External Clock
Frequency 64
64
Duty Cycle
45:55
45:55
LOGIC INPUTS
All Inputs Except SCLK, DIN and CLK
2
V
INL
, Input Low Voltage
0.8
V max
DV
DD
= 5 V
0.4
V max
DV
DD
= 3 V
V
INH
, Input High Voltage
2.0
V min
DV
DD
= 3 V or 5 V
SCLK and DIN (Schmitt-Triggered
Input)
2
V
T
(+)
1.4/2
V min/V max
DV
DD
= 5 V
V
T
()
0.8/1.4
V min/V max
DV
DD
= 5 V
V
T
(+) V
T
()
0.3/0.85
V min/V max
DV
DD
= 5 V
V
T
(+)
0.9/2
V min/V max
DV
DD
= 3 V
V
T
()
0.4/1.1
V min/V max
DV
DD
= 3 V
V
T
(+) - V
T
()
0.3/0.85
V min/V max
DV
DD
= 3 V
CLK
2
V
INL
, Input Low Voltage
0.8
V max
DV
DD
= 5 V
V
INL
, Input Low Voltage
0.4
V max
DV
DD
= 3 V
V
INH
, Input High Voltage
3.5
V min
DV
DD
= 5 V
AD7794
Preliminary Technical Data
REV.PrE 6/04 | Page 8
Parameter AD7794B
Unit
Test
Conditions/Comments
V
INH
, Input High Voltage
2.5
V min
DV
DD
= 3 V
Input Currents
1
A max
V
IN
= DV
DD
or GND
Input Capacitance
10
pF typ
All Digital Inputs
LOGIC OUTPUTS (Including CLK)
V
OH
, Output High Voltage
2
DV
DD
0.6
V min
DV
DD
= 3 V, I
SOURCE
= 100 A
V
OL
, Output Low Voltage
2
0.4
V
max
DV
DD
= 3 V, I
SINK
= 100 A
V
OH
, Output High Voltage
2
4
V min
DV
DD
= 5 V, I
SOURCE
= 200 A
V
OL
, Output Low Voltage
2
0.4
V
max
DV
DD
= 5 V, I
SINK
= 1.6 mA (DOUT/RDY)/800 A (CLK)
Floating-State Leakage Current
1
A max
Floating-State Output Capacitance
10
pF typ
Data Output Coding
Offset Binary
SYSTEM CALIBRATION
2
V
max
Full-Scale Calibration Limit
1.05 x FS
V max
Zero-Scale Calibration Limit
-1.05 x FS
Input Span
0.8 x FS
V min
V min
2.1 x FS
V min
POWER REQUIREMENTS
7
Power Supply Voltage
AV
DD
GND
2.7/5.25
V min/max
DV
DD
GND
2.7/5.25
V min/max
Power Supply Currents
I
DD
Current
150
A max
125 A typ, Unbuffered Mode, Ext. Reference
175
A max
150 A typ, Buffered Mode, In-Amp Bypassed, Ext
Ref
380
A max
330 A typ, In-Amp used, Ext. Ref
450
A max
400 A typ, In-Amp used, Int Ref
I
DD
(Power-Down Mode)
1
A max
1
Temperature Range 40C to +105C.
2
Specification is not production tested but is supported by characterization data at initial product release.
3
Following a self-calibration, this error will be in the order of the noise for the programmed gain and update rate selected. A system calibration will completely remove
this error.
4
Recalibration at any temperature will remove these errors.
5
Full-scale error applies to both positive and negative full-scale and applies at the factory calibration conditions (AV
DD
= 4 V).
6
FS[3:0] are the four bits used in the mode register to select the output word rate.
7
Digital inputs equal to DV
DD
or GND.
Preliminary Technical Data
AD7794
REV.PrE 6/04 | Page 9
TIMING CHARACTERISTICS
8, 9
Table 2. (AV
DD
= 2.7 V to 5.25 V; DV
DD
= 2.7 V to 5.25; GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DV
DD
, unless otherwise
noted.)
Parameter
Limit at T
MIN
, T
MAX
(B Version)
Unit Conditions/Comments
t
3
100
ns min
SCLK High Pulsewidth
t
4
100
ns min
SCLK Low Pulsewidth
Read Operation
t
1
0
ns min
CS Falling Edge to DOUT/RDY Active Time
60
ns max
DV
DD
= 4.75 V to 5.25 V
80
ns max
DV
DD
= 2.7 V to 3.6 V
t
2
10
0
ns min
SCLK Active Edge to Data Valid Delay
11
60
ns max
DV
DD
= 4.75 V to 5.25 V
80
ns max
DV
DD
= 2.7 V to 3.6 V
t
5
12, 13
10
ns min
Bus Relinquish Time after CS Inactive Edge
80
ns max
t
6
100
ns max
SCLK Inactive Edge to CS Inactive Edge
t
7
10
ns min
SCLK Inactive Edge to DOUT/RDY High
Write Operation
t
8
0
ns min
CS Falling Edge to SCLK Active Edge Setup Time
11
t
9
30
ns min
Data Valid to SCLK Edge Setup Time
t
10
25
ns min
Data Valid to SCLK Edge Hold Time
t
11
0
ns min
CS Rising Edge to SCLK Edge Hold Time
8
Sample tested during initial release to ensure compliance. All input signals are specified with t
R
= t
F
= 5 ns (10% to 90% of DV
DD
) and timed from a voltage level of 1.6 V.
9
See Figure 2 and Figure 3.
10
These numbers are measured with the load circuit of
Figure 1 and defined as the time required for the output to cross the V
OL
or V
OH
limits.
11
SCLK active edge is falling edge of SCLK.
12
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of
Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the
timing characteristics are the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances.
13
RDY returns high after a read of the ADC. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY is high,
although care should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read
only once.
AD7794
Preliminary Technical Data
REV.PrE 6/04 | Page 10
+1.6 V
50 pF
Figure 1. Load Circuit for Timing Characterization
t
2
t
3
t
4
t
1
t
6
t
5
t
7
04227-0-003
CS (I)
DOUT/RDY (O)
SCLK (I)
I = INPUT, O = OUTPUT
MSB
LSB
Figure 2. Read Cycle Timing Diagram
04227-0-004
I = INPUT, O = OUTPUT
CS (I)
SCLK (I)
DIN (I)
MSB
LSB
t
8
t
9
t
10
t
11
Figure 3. Write Cycle Timing Diagram
Preliminary Technical Data
AD7794
REV.PrE 6/04 | Page 11
ABSOLUTE MAXIMUM RATINGS
Table 3. (T
A
= 25C, unless otherwise noted.)
Parameter Rating
AV
DD
to GND
0.3 V to +7 V
DV
DD
to GND
0.3 V to +7 V
Analog Input Voltage to GND
0.3 V to AV
DD
+ 0.3 V
Reference Input Voltage to GND
0.3 V to AV
DD
+ 0.3 V
Digital Input Voltage to GND
0.3 V to AV
DD
+ 0.3 V
Digital Output Voltage to GND
0.3 V toA V
DD
+ 0.3 V
AIN/Digital Input Current
10 mA
Operating Temperature Range
40C to +105C
Storage Temperature Range
65C to +150C
Maximum Junction Temperature
150C
TSSOP
JA
Thermal Impedance
97.9C/W
JC
Thermal Impedance
14C/W
Lead Temperature, Soldering
Vapor Phase (60 sec)
215C
Infrared (15 sec)
220C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
AD7794
Preliminary Technical Data
REV.PrE 6/04 | Page 12
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
9
16
AIN2(+)
AIN5(-)/IOUT1
10
11
12
15
14
13
AIN2(-)
AIN3(+)
AIN3(-)
AIN5(+)/IOUT2
REFIN1(-)
REFIN1(+)
5
20
AIN6(+)/P1
GND
6
7
8
19
18
17
AIN6(-)/P2
AIN1(+)
AIN1(-)
PSW
AIN4(-)/REFIN2(-)
AIN4(+)/REFIN2(+)
3
4
22
21
CS
NC
DVDD
AVDD
1
2
24
23
SCLK
CLK
DIN
DOUT/RDY
AD7794
TOP VIEW
(Not To Scale)
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin
No.
Mnemonic
Function
1 SCLK
Serial Clock Input for Data Transfers to and from the ADC. The SCLK has a Schmitt-triggered input, making the
interface suitable for opto-isolated applications. The serial clock can be continuous with all data transmitted in
a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information being trans-
mitted to or from the ADC in smaller batches of data.
2 CLK
Clock In/Clock Out. The internal clock can be made available at this pin. Alternatively, the internal clock can
be disabled and the ADC can be driven by an external clock. This allows several ADCs to be driven from a
common clock, allowing simultaneous conversions to be performed.
3
CS
Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC in
systems with more than one device on the serial bus or as a frame synchronization signal in communicating
with the device. CS can be hardwired low, allowing the ADC to operate in 3-wire mode with SCLK, DIN, and
DOUT used to interface with the device.
4 NC
No
Connect
5 AIN6(+)/P1
Analog Input/Digital Output pin. AIN6(+) is the positive terminal of the differential analog input pair
AIN6(+)/AIN6(-). Alternatively, this pin can function as a general purpose output bit referenced between AV
DD
and GND
6 AIN6()/P2
Analog Input/ Digital Output pin. AIN6() is the negative terminal of the differential analog input pair
AIN6(+)/AIN6(-). Alternatively, this pin can function as a general purpose output bit referenced between AV
DD
and GND
7
AIN1(+)
Analog Input. AIN1(+) is the positive terminal of the differential analog input pair AIN1(+)/AIN1(-).
8
AIN1(-)
Analog Input. AIN1() is the negative terminal of the differential analog input pair AIN1(+)/AIN1(-).
9
AIN2(+)
Analog Input. AIN2(+) is the positive terminal of the differential analog input pair AIN2(+)/AIN2(-).
10
AIN2(-)
Analog Input. AIN2() is the negative terminal of the differential analog input pair AIN2(+)/AIN2(-).
11
AIN3(+)
Analog Input. AIN3(+) is the positive terminal of the differential analog input pair AIN3(+)/AIN3(-).
12
AIN3(-)
Analog Input. AIN3() is the negative terminal of the differential analog input pair AIN3(+)/AIN3(-).
13 REFIN1(+)
Positive Reference Input. An external reference can be applied between REFIN1(+) and REFIN1(-). REFIN1(+)
can lie anywhere between V
DD
and GND + 0.1 V. The nominal reference voltage (REFIN1(+) REFIN1()) is 2.5
V, but the part functions with a reference from 0.1 V to AV
DD
.
14
REFIN1(-)
Negative Reference Input. This reference input can lie anywhere between GND and AV
DD
0.1 V.
15 AIN5(+)/IOUT2
Analog
Input/Output of Internal Excitation Current Source.
AIN5(+) is the positive terminal of the differential analog input pair AIN5(+)/AIN5(-).
Alternatively, the internal excitation current source can be made available at this pin. The excitation current
source is programmable so that the current can be 10 uA, 200 uA or 1 mA. Either IEXC1 or IEXC2 can be
switched to this output
16
AIN5(-)/IOUT1
Analog Input/Output of Internal Excitation Current Source.
Preliminary Technical Data
AD7794
REV.PrE 6/04 | Page 13
Pin
No.
Mnemonic
Function
AIN5(-) is the negative terminal of the differential analog input pair AIN5(+)/AIN5(-).
Alternatively, the internal excitation current source can be made available at this pin. The excitation current
source is programmable so that the current can be 10 uA, 200 uA or 1 mA. Either IEXC1 or IEXC2 can be
switched to this output.
17 AIN4(+)/REFIN2(+)
Analog
Input/Positive Reference Input.
AIN4(+) is the positive terminal of the differential analog input pair AIN4(+)/AIN4(-).
This pin can aso function as a reference input. REFIN2(+) can lie anywhere between AV
DD
and GND + 0.1 V.
The nominal reference voltage (REFIN2(+) REFIN2()) is 2.5 V, but the part functions with a reference from 0.1
V to AV
DD
.
18 AIN4(-)/REFIN2(-) Analog
Input/Negative Reference Input.
AIN4(-) is the negative terminal of the differential analog input pair AIN4(+)/AIN4(-).
This pin also functions as the negative reference input for REFIN2. This reference input can lie anywhere
between GND and AV
DD
0.1 V.
19
PSW
Low Side Power Switch to GND.
20
GND
Ground Reference Point.
21 AV
DD
Supply Voltage, 2.7 V to 5.25 V.
22 D
V
DD
Serial Interface Supply Voltage, 2.7 V to 5.25 V. DV
DD
is independent of AV
DD
. Therefore, the serial interface can
be operated at 3 V with AV
DD
at 5 V or vice versa.
23
DOUT/RDY
Serial Data Output/Data Ready Output. DOUT/RDY serves a dual purpose . It functions as a serial data output pin
to access the output shift register of the ADC. The output shift register can contain data from any of the
on-chip data or control registers. In addition, DOUT/RDY operates as a data ready pin,
going low to indicate the completion of a conversion. If the data is not read after the conversion, the pin will go
high before the next update occurs.
The DOUT/RDY falling edge can be used as an interrupt to a processor, indicating that valid data is available.
With an external serial clock, the data can be read using the DOUT/RDY pin. With CS low, the data/control word
informa-tion is placed on the DOUT/RDY pin on the SCLK falling edge and is valid on the SCLK rising edge.
The end of a conversion is also indicated by the RDY bit in the status register. When CS is high, the DOUT/RDY
pin is three-stated but the RDY bit remains active.
24 DIN
Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the control
registers within the ADC, the register selection bits of the communications register identifying the appropriate
register.
AD7794
Preliminary Technical Data
REV.PrE 6/04 | Page 14
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Preliminary Technical Data
AD7794
REV.PrE 6/04 | Page 15
ON-CHIP REGISTERS
The ADC is controlled and configured via a number of on-chip registers, which are described on the following pages. In the following
descriptions, set implies a Logic 1 state and cleared implies a Logic 0 state, unless otherwise stated.
COMMUNICATIONS REGISTER (RS2, RS1, RS0 = 0, 0, 0)
The communications register is an 8-bit write-only register. All communications to the part must start with a write operation to the com-
munications register. The data written to the communications register determines whether the next operation is a read or write operation,
and to which register this operation takes place. For read or write operations, once the subsequent read or write operation to the selected
register is complete, the interface returns to where it expects a write operation to the communications register. This is the default state of
the interface and, on power-up or after a reset, the ADC is in this default state waiting for a write operation to the communications regis-
ter. In situations where the interface sequence is lost, a write operation of at least 32 serial clock cycles with DIN high returns the ADC to
this default state by resetting the entire part. Table 5 outlines the bit designations for the communications register. CR0 through CR7 indi-
cate the bit location, CR denoting the bits are in the communications register. CR7 denotes the first bit of the data stream. The number in
brackets indicates the power-on/reset default status of that bit.
CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0
WEN(0) R/W(0)
RS2(0)
RS1(0)
RS0(0)
CREAD(0)
0(0)
0(0)
Table 5. Communications Register Bit Designations
Bit Location
Bit Name
Description
CR7
WEN
Write Enable Bit. A 0 must be written to this bit so that the write to the communications register actually
occurs. If a 1 is the first bit written, the part will not clock on to subsequent bits in the register. It will stay
at this bit location until a 0 is written to this bit. Once a 0 is written to the WEN bit, the next seven bits
will be loaded to the communications register.
CR6
R/W
A 0 in this bit location indicates that the next operation will be a write to a specified register. A 1 in this
position indicates that the next operation will be a read from the designated register.
CR5CR3 RS2RS0 Register Address Bits. These address bits are used to select which of the ADC's registers are being
selected during this serial interface communication. See Table 6.
CR2
CREAD
Continuous Read of the Data Register. When this bit is set to 1 (and the data register is selected), the
serial interface is configured so that the data register can be continuously read, i.e., the contents of the
data register are placed on the DOUT pin automatically when the SCLK pulses are applied. The commu-
nications register does not have to be written to for data reads. To enable continuous read mode, the
instruction 01011100 must be written to the communications register. To exit the continuous read
mode, the instruction 01011000 must be written to the communications register while the RDY pin is
low. While in continuous read mode, the ADC monitors activity on the DIN line so that it can receive the
instruction to exit continuous read mode. Additionally, a reset will occur if 32 consecutive 1s are seen on
DIN. Therefore, DIN should be held low in continuous read mode until an instruction is to be written to
the device.
CR1CR0
0
These bits must be programmed to logic 0 for correct operation.
Table 6. Register Selection
RS2 RS1 RS0 Register
Register
Size
0
0
0
Communications Register during a Write Operation
8-Bit
0
0
0
Status Register during a Read Operation
8-Bit
0 0 1 Mode
Register
16-Bit
0 1 0 Configuration
Register
16-Bit
0 1 1 Data
Register
24-Bit
1 0 0 ID
Register
8-Bit
1 0 1 IO
Register
8-Bit
1 1 0 Offset
Register
24-Bit
1 1 1 Full-ScaleRegister
24-Bit
AD7794
Preliminary Technical Data
REV.PrE 6/04 | Page 16
STATUS REGISTER (RS2, RS1, RS0 = 0, 0, 0; POWER-ON/RESET = 0x88)
The status register is an 8-bit read-only register. To access the ADC status register, the user must write to the communications register,
select the next operation to be a read, and load bits RS2, RS1 and RS0 with 0. Table 7 outlines the bit designations for the status register.
SR0 through SR7 indicate the bit locations, SR denoting the bits are in the status register. SR7 denotes the first bit of the data stream. The
number in brackets indicates the power-on/reset default status of that bit.
SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0
RDY(1)
ERR(0)
NOREF(0)
0(0)
1(1)
CH2(0)
CH1(0)
CH0(0)
Table 7. Status Register Bit Designations
Bit Location
Bit Name
Description
SR7
RDY
Ready bit for ADC. Cleared when data is written to the ADC data register. The RDY bit is set automatically
after the ADC data register has been read or a period of time before the data register is updated with a
new conversion result to indicate to the user not to read the conversion data. It is also set when the part
is placed in power-down mode. The end of a conversion is indicated by the DOUT/RDY pin also. This pin
can be used as an alternative to the status register for monitoring the ADC for conversion data.
SR6
ERR
ADC Error Bit. This bit is written to at the same time as the RDY bit. Set to indicate that the result written
to the ADC data register has been clamped to all 0s or all 1s. Error sources include overrange,
underrange or the absence of a reference voltage. Cleared by a write operation to start a conversion.
SR5 NOREF
No External Reference Bit. Set to indicate that the selected reference (REFIN1 or REFIN2) is at a voltage
that is below a specified threshold. When set, conversion results are clamped to all ones.
Cleared to indicate that a valid reference is applied to the selected reference pins.
The NOXREF bit is enabled by setting the REF_DET bit in the Configuration register to 1. The ERR bit is
also set if the voltage applied to the selected reference input is invalid.
SR4
0
This bit is automatically cleared.
SR3
1
This bit is automatically set.
SR2SR0
CH2CH0
These bits indicate which channel is being converted by the ADC.
MODE REGISTER (RS2, RS1, RS0 = 0, 0, 1; POWER-ON/RESET = 0x000A)
The mode register is a 16-bit register from which data can be read or to which data can be written. This register is used to select the oper-
ating mode, the update rate and the clock source. Table 8 outlines the bit designations for the mode register. MR0 through MR15 indicate
the bit locations, MR denoting the bits are in the mode register. MR15 denotes the first bit of the data stream. The number in brackets
indicates the power-on/reset default status of that bit. Any write to the setup register resets the modulator and filter and sets the RDY bit.
MR15
MR14
MR13
MR12
MR11
MR10
MR9
MR8
MD2(0)
MD1(0)
MD0(0)
PSW(0)
0(0)
0(0)
0(0)
0(0)
MR7
MR6
MR5
MR4
MR3
MR2
MR1
MR0
CLK1(0)
CLK0(0)
0(0)
CHOP-DIS
(0)
FS3(1) FS2(0) FS1(1) FS0(0)
Table 8. Mode Register Bit Designations
Bit Location
Bit Name
Description
MR15MR13
MD2MD0
Mode Select Bits. These bits select the operational mode of the AD7794 (See
Table 9).
MR12
PSW
Power Switch Control Bit.
Set by user to close the power switch PSW to GND. The power switch can sink up to 20 mA.
Cleared by user to open the power switch.
When the ADC is placed in power-down mode, the power switch is opened.
MR11-MR8
0
These bits must be programmed with a Logic 0 for correct operation.
MR7-MR6 CLK1-CLK0
These bits are used to select the clock source for the AD7794. Either the on-chip 64 kHz clock can be
used or an external clock can be used. The ability to use an external clock is useful as it allows several
AD7794 devices to be synchronised. Also, 50 Hz/60 Hz rejection is improved when an accurate external
clock drives the AD7794.
Preliminary Technical Data
AD7794
REV.PrE 6/04 | Page 17
Bit Location
Bit Name
Description
CLK1 CLK0 ADC
Clock
Source
0
0
Internal 64 kHz Clock, Internal Clock is not available at the CLK pin
0
1
Internal 64 kHz Clock. This clock is made available at the CLK pin
1
0
External 64 kHz Clock used. The external clock can have a 45:55 duty cycle.
1 1 External Clock used. This external clock is divided by 2 within the AD7794. This
allows the user to supply a clock which has a duty cycle worse than a 45:55 duty
cycle to the AD7794, for example, a 128 kHz clock.
MR5
0
This bit must be programmed with a Logic 0 for correct operation.
MR4 CHOP-DIS
This bit is used to enable or disable chopping. On power-up or following a reset, CHOP-DIS is cleared so
chopping is enabled. When CHOP-DIS is set, chopping is disabled.
MR3-MR0
FS3-FS0
Filter Update Rate Select Bits (see Table 10).
Table 9. Operating Modes
MD2
MD1
MD0
Mode
0
0
0
Continuous Conversion Mode (Default).
In continuous conversion mode, the ADC continuously performs conversions and places the result in the data
register. RDY goes low when a conversion is complete. The user can read these conversions by placing the
device in continuous read mode whereby the conversions are automatically placed on the DOUT line when
SCLK pulses are applied. Alternatively, the user can instruct the ADC to output the conversion by writing to
the communications register. After power-on, the first conversion is available after a period 2/ f
ADC
when
chopping is enabled or 1/ f
ADC
when chopping is disabled. Subsequent conversions are available at a
frequency of f
ADC
with chopping either enabled or disabled,
0
0
1
Single Conversion Mode.
In single conversion mode, the ADC is placed in power-down mode when conversions are not being
performed. When single conversion mode is selected, the ADC powers up and performs a single conversion,
which occurs after a period 2/f
ADC
when chopping is enabled or 1/ f
ADC
when chopping is disabled. The
conversion result in placed in the data register, RDY goes low, and the ADC returns to power-down mode.
The conversion remains in the data register and RDY remains active (low) until the data is read or another
conversion is performed.
0
1
0
Idle Mode.
In Idle Mode, the ADC Filter and Modulator are held in a reset state although the modulator clocks are still
provided
0
1
1
Power-Down Mode.
In power down mode, all the AD7794 circuitry is powered down including the current sources, power switch,
burnout currents, bias voltage generator and CLKOUT circuitry.
1
0
0
Internal Zero-Scale Calibration.
An internal short is automatically connected to the enabled channel. A calibration takes 2 conversion cycles
to complete when chopping is enabled and 1 conversion cycle when chopping is disabled. RDY goes high
when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle
mode following a calibration. The measured offset coefficient is placed in the offset register of the selected
channel
1
0
1
Internal Full-Scale Calibration.
The fullscale input voltage is automatically connected to the selected analog input for this calibration.
The full-scale error of the AD7794 is calbrated at a gain of 1 using the internal reference in the factory. When
a channel is operated with a gain of 1 and the internal reference is selected, this factory-calibrated value is
loaded into the full-scale register when a full-scale calibration is initiated.
When an external reference is selected at a gain of 1, an internal fullscale calibration can be performed. When
the gain equals 1, a calibration takes 2 conversion cycles to complete when chopping is enabled and 1
conversion cycle when chopping is disabled.
For higher gains, 4 conversion cycles are required to perform the fullscale calibration when chopping is
enabled and 2 conversion cycles when chopping is disabled.
RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is
placed in idle mode following a calibration. The measured fullscale coefficient is placed in the fullscale
register of the selected channel.
Internal full-scale calibrations cannot be performed when the gain equals 128. With this gain setting, a
system full-scale calibration can be performed.
AD7794
Preliminary Technical Data
REV.PrE 6/04 | Page 18
A fullscale calibration is required each time the gain of a channel is changed.
1
1
0
System Offset Calibration.
User should connect the system zero-scale input to the .channel input pins as selected by the CH2-CH0 bits.
A system offset calibration takes 2 conversion cycles to complete when chopping is enabled and one
conversion cycle when chopping is disabled. RDY goes high when the calibration is initiated and returns low
when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured
offset coefficient is placed in the offset register of the selected channel.
1
1
1
System Full-Scale Calibration.
User should connect the system full-scale input to the .channel input pins as selected by the CH2-CH0 bits.
A calibration takes 2 conversion cycles to complete when chopping is enabled and one conversion cycle
when chopping is disabled.. RDY goes high when the calibration is initiated and returns low when the
calibration is complete. The ADC is placed in idle mode following a calibration. The measured fullscale
coefficient is placed in the fullscale register of the selected channel.
A fullscale calibration is required each time the gain of a channel is changed.
Table 10.
Update Rates Available (Chopping Enabled)
FS3
FS2 FS1
FS0 f
ADC
(Hz)
Tsettle
(ms)
Rejection@ 50 Hz / 60 Hz (Internal Clock)
0 0 0
0
x
x
0
0
0
1
500
5
0 0 1
0
250
8
0 0 1
1
125
16
0 1 0
0
62.5
32
0 1 0
1
50
40
0 1 1
0
41.6
48
0 1 1 1 33.3
60
1 0 0 0 19.6
101
90
dB
(60
Hz
only)
1 0 0 1 16.6
120
84
dB
(50
Hz
only)
1
0
1
0
16.6
120
70 dB (50 Hz and 60 Hz)
1
0
1
1
12.5
160
67 dB (50 Hz and 60 Hz)
1
1
0
0
10
200
69 dB (50 Hz and 60 Hz)
1
1
0
1
8.33
240
73 dB (50 Hz and 60 Hz)
1
1
1
0
6.25
320
74 dB (50 Hz and 60 Hz)
1
1
1
1
4.17
480
79 dB (50 Hz and 60 Hz)
With chopping disabled, the update rates remain unchanged but the settling time for each update rate is reduced by a factor of 2. The
rejection at 50 Hz/60 Hz for a 16.6 Hz update rate degrades to 60 dB.
CONFIGURATION REGISTER (RS2, RS1, RS0 = 0, 1, 0; POWER-ON/RESET = 0x0710)
The configuration register is a 16-bit register from which data can be read or to which data can be written. This register is used to configure
the ADC for unipolar or bipolar mode, enable or disable the buffer, enable or disable the burnout currents, select the gain and select the ana-
log input channel. Table 11 outlines the bit designations for the filter register. CON0 through CON15 indicate the bit locations, CON
denoting the bits are in the configuration register. CON15 denotes the first bit of the data stream. The number in brackets indicates the
power-on/reset default status of that bit.
CON15
CON14 CON13 CON12 CON11
CON10
CON9
CON8
VBIAS1(0)
VBIAS0(0)
BO(0)
U/B (0)
0(0)
G2(1)
G1(1)
G0(1)
CON7
CON6
CON5
CON4
CON3
CON2
CON1
CON0
REFSEL1(0)
REFSEL0(0)
REF_DET(0)
BUF(1) CH3(0) CH2(0) CH1(0) CH0(0)
Preliminary Technical Data
AD7794
REV.PrE 6/04 | Page 19
Table 11. Configuration Register Bit Designations
Bit
Location
Bit Name
Description
CON15
CON14
0
Bias Voltage Generator Enable. The negative terminal of the analog inputs can b e biased up to VDD/2.
VBIAS1 VBIAS0 Bias
Voltage
0
0
Bias Voltage Generator Disabled
0
1
Bias Voltage Generator connected to AIN1(-)
1
0
Bias Voltage Generator connected to AIN2(-)
1
1
Bias Voltage Generator connected to AIN3(-)
CON13
BO
This bit must be programmed with a Logic 0 for correct operation.
Burnout Current Enable Bit. When this bit is set to 1 by the user, the 100 nA current sources in the signal
path are enabled. When BO = 0, the burnout currents are disabled. The burnout currents can be enabled
only when the buffer or in-amp is active.
CON12
U/B Unipolar/Bipolar
Bit.
Set by user to enable unipolar coding, i.e., zero differential input will result in
0x000000 output and a full-scale differential input will result in 0xFFFFFF output. Cleared by the user to
enable bipolar coding. Negative full-scale differential input will result in an output code of 0x000000,
zero differential input will result in an output code of 0x800000, and a positive full-scale differential
input will result in an output code of 0xFFFFFF.
CON11
0
This bit must be programmed with a Logic 0 for correct operation.
CON10-
CON8
G2-G0
Gain Select Bits.
Written by the user to select the ADC input range as follows
G2
G1
G0
Gain
ADC Input Range (2.5V Reference)
0
0
0
1 (In-Amp not used)
2.5 V
0
0
1
2 (In-Amp not used)
1.25 V
0 1 0 4
625
mV
0 1 1 8
312.5
mV
1 0 0 16
156.2
mV
1 0 1 32
78.125
mV
1 1 0 64
39.06
mV
1 1 1 128
19.53
mV
CON7-
CON6
REFSEL1/REFSEL0 Reference Select Bits. The reference source for the ADC is selected using these bits.
REFSEL1 REFSEL0 Reference
Source
0
0
External Reference applied between REFIN1(+) and REFIN1(-)
0
1
External Reference applied between REFIN2(+) and REFIN2(-)
1
0
Internal 1.17 V Reference
1 1 Reserved
CON5
REF_DET
Enables the Reference Detect Function.
When set, the NOXREF bit in the status register indicates when the external reference being used by the
ADC is open circuit or less than 0.5 V.
When cleared, the reference detect function is disabled.
CON4 BUF
Configures the ADC for buffered or unbuffered mode of operation. If cleared, the ADC operates in
unbuffered mode, lowering the power consumption of the device. If set, the ADC operates in buffered
mode, allowing the user to place source impedances on the front end without contributing gain errors
to the system. For gains of 1 and 2, the buffer can be enabled or disabled. For higher gains, the buffer is
automatically enabled.
CON3-
CON0
CH3-CH0 Channel
Select
bits.
Written by the user to select the active analog input channel to the ADC.
CH3 CH2 CH1 CH0 Channel
Calibration
Pair
0 0 0 0 AIN1(+)
AIN1(-) 0
0 0 0 1 AIN2(+)
AIN2(-) 1
0 0 1 0 AIN3(+)
AIN3(-) 2
0 0 1 1 AIN4(+)
AIN4(-) 3
AD7794
Preliminary Technical Data
REV.PrE 6/04 | Page 20
Bit
Location
Bit Name
Description
0 1 0 0 AIN5(+)
AIN5(-) 3
0 1 0 1 AIN6(+)
AIN6(-) 3
0 1 1 0 Temp
Sensor
Automatically selects the internal
reference and sets the gain to 1
0 1 1 1 VDD
Monitor
Automatically selects the internal 1.17 V
reference and sets the gain to 1/6
1 0 0 0 AIN1(-)
AIN1(-) 0
1 0 0 1 Reserved
1 0 1 0 Reserved
1 0 1 1 Reserved
1 1 0 0 Reserved
1 1 0 1 Reserved
1 1 1 0 Reserved
1 1 1 1 Reserved
DATA REGISTER (RS2, RS1, RS0 = 0, 1, 1; POWER-ON/RESET = 0x000000)
The conversion result from the ADC is stored in this data register. This is a read-only register. On completion of a read operation from
this register, the RDY bit/pin is set.
ID REGISTER (RS2, RS1, RS0 = 1, 0, 0; POWER-ON/RESET = 0xXF)
The Identification Number for the AD7794 is stored in the ID register. This is a read-only register.
IO REGISTER (RS2, RS1, RS0 = 1, 0, 1; POWER-ON/RESET = 0x00)
The I/O register is an 8-bit register from which data can be read or to which data can be written. This register is used to enable the excitation
currents and select the value of the excitation currents. Table 12 outlines the bit designations for the IO register. IO0 through IO7 indicate
the bit locations, IO denoting the bits are in the IO register. IO7 denotes the first bit of the data stream. The number in brackets indicates the
power-on/reset default status of that bit.
IO7
IO6
IO5
IO4
IO3
IO2
IO1
IO0
0(0)
IOEN(0)
IO2DAT(0)
IO1DAT(0)
IEXCDIR1(0) IEXCDIR0(0) IEXCEN1(0) IEXCEN0(0)
Table 12 Filter Register Bit Designations
Bit Location
Bit Name
Description
IO7
0
This bit must be programmed with a Logic 0 for correct operation.
IO6
IOEN
Configures the pins AIN6(+)/P2 and AIN6(-)/P2 are analog input pins or digital output pins.
When this bit is set, the pins are configured as digital output pins P1 and P2.
When this bit is cleared, these pins are configured as analog input pins AIN6(+) and AIN6(-).
IO5-IO4 IO2DAT/IO1DAT
P2/P1
Data.
When IOEN is set, the data for the digital output pins P1 and P2 is written to bits IO2DAT and IO1DAT.
IO3-IO2
IEXCDIR1
IEXCDIR0
Direction of Current Sources Select bits.
IEXCDIR1
IEXCDIR0
Current Source Direction
0 0 Current Source IEXC1 connected to pin IOUT1, Current Source IEXC2
connected to pin IOUT2
0 1 Current Source IEXC1 connected to pin IOUT2, Current Source IEXC2
connected to pin IOUT1
1 0 Both Current Sources connected to pin IOUT1. Permitted only when the
current sources are set to 10 uA or 200 uA
1 1 Both Current Sources connected to pin IOUT2. Permitted only when the
current sources are set to 10 uA or 200 uA
IO3-IO2
IEXCEN1
These bits are used to enable and disable the current sources along with selecting the value of the
Preliminary Technical Data
AD7794
REV.PrE 6/04 | Page 21
Bit Location
Bit Name
Description
IEXCEN0
excitation currents.
IEXCEN1
IEXCEN0
Current Source Value
0
0
Excitation Currents Disabled
0 1 10
uA
1 0 200
uA
1 1 1
mA
OFFSET REGISTER (RS2, RS1, RS0 = 1, 1, 0; POWER-ON/RESET = 0x800000)
The offset register holds the offset calibration coefficient for the ADC. The power-on-reset value of the internal zero-scale calibration
coefficient register is 800000 hex. The AD7794 has 4 offset registers. Channels AIN1 to AIN3 have dedicated offset registers while chan-
nels AIN4, AIN5 and AIN6 share an offset register. Each of these registers is a 24-bit read/write register. This register is used in
conjunction with its associated full-scale register to form a register pair. The power-on-reset value is automatically overwritten if an in-
ternal or system zero-scale calibration is initiated by the user. The AD7794 must be placed in power down mode or idle mode when
writing to the offset register.
FULL-SCALE REGISTER (RS2, RS1, RS0 = 1, 1, 1; POWER-ON/RESET = 0x5XXXX5)
The full-scale registers is a 24-bit register that holds the full-scale calibration coefficient for the ADC. The AD77794 has 4 full-scale
registers. Channels AIN1, AIN2 and AIN3 have dedicated full-scale registers while channels AIN4, AIN5 and AIN6 share a register. The
full-scale registers are read/write registers. However, when writing to the full-scale registers, the ADC must be placed in power down
mode or idle mode. These registers are configured on power-on with factory-calibrated internal full-scale calibration coefficients, the
factory calibration being performed with the gain set to 1 and using the internal reference. Therefore, every device will have different
default coefficients. These default values are used when the device is operated with a gain of 1 and when the internal reference is selected.
For other gains or when the external reference is used at a gain of 1, these default coefficients will be automatically overwritten if an
internal or system full-scale calibration is initiated by the user. A full-scale calibration should be performed when the gain is changed.
TYPICAL APPLICATION (FLOWMETER)
GND
AVDD
AD7794
SERIAL
INTERFACE
AND
CONTROL
LOGIC
INTERNAL
CLOCK
CLK
SIGMA DELTA
ADC
IN-AMP
DOUT/RDY
DIN
SCLK
CS
DVDD
AIN1(+)
AIN1(-)
VDD
GND
VDD
PSW
GND
AIN3(+)
AIN2(+)
AIN2(-)
IN+
IN-
OUT+
OUT-
IN+
IN-
OUT+
OUT-
VDD
REFIN1(+)
REFIN1(-)
AIN3(-)
MUX
RCM
IOUT1
PR04854-0-6/04(PrE)
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