AD7328 8-Channel, Software-Selectable True Bipolar Input, 12-Bit Plus Sign ADC Data Sheet (Rev. 0)
8-Channel, Software-Selectable True
Bipolar Input, 12-Bit Plus Sign ADC
AD7328
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2005 Analog Devices, Inc. All rights reserved.
FEATURES
12-bit plus sign SAR ADC
True bipolar input ranges
Software-selectable input ranges
10 V, 5 V, 2.5 V, 0 V to 10 V
1 MSPS throughput rate
Eight analog input channels with channel sequencer
Single-ended, true differential, and pseudo differential
analog input capability
High analog input impedance
Low power: 21 mW
Temperature indicator
Full power signal bandwidth: 22 MHz
Internal 2.5 V reference
High speed serial interface
Power-down modes
20-lead TSSOP package
iCMOS
TM
process technology
GENERAL DESCRIPTION
The AD7328
1
is an 8-channel, 12-bit plus sign successive
approximation ADC designed on the iCMOS (industrial
CMOS) process. iCMOS is a process combining high voltage
CMOS and low voltage CMOS. It enables the development of a
wide range of high performance analog ICs capable of 33 V
operation in a footprint that no previous generation of high
voltage parts could achieve. Unlike analog ICs using conven-
tional CMOS processes, iCMOS components can accept bipolar
input signals while providing increased performance, dramatically
reducing power consumption, and having a reduced package size.
The AD7328 can accept true bipolar analog input signals. The
AD7328 has four software-selectable input ranges, 10 V, 5 V,
2.5 V, and 0 V to 10 V. Each analog input channel can be indepen-
dently programmed to one of the four input ranges. The analog
input channels on the AD7328 can be programmed to be single-
ended, true differential, or pseudo differential.
The ADC contains a 2.5 V internal reference. The AD7328 also
allows for external reference operation. If a 3 V reference is applied
to the REFIN/OUT pin, the AD7328 can accept a true bipolar
12 V analog input. Minimum 12 V V
DD
and V
SS
supplies are
required for the 12 V input range. The ADC has a high speed
serial interface that can operate at throughput rates up to 1 MSPS.
FUNCTIONAL BLOCK DIAGRAM
V
IN
0
DOUT
SCLK
CS
DIN
V
DRIVE
V
IN
1
V
IN
2
V
IN
3
V
IN
4
V
IN
5
V
IN
6
V
IN
7
V
DD
REFIN/OUT
V
CC
AGND
V
SS
DGND
CONTROL LOGIC
AND REGISTERS
13-BIT
SUCCESSIVE
APPROXIMATION
ADC
T/H
2.5V
VREF
I/P
MUX
CHANNEL
SEQUENCER
AD7328
04852-
001
TEMPERATURE
INDICATOR
Figure 1.
PRODUCT HIGHLIGHTS
1.
The AD7328 can accept true bipolar analog input signals,
10 V, 5 V, 2.5 V, and 0 V to 10 V unipolar signals.
2.
The eight analog inputs can be configured as eight single-
ended inputs, four true differential inputs, four pseudo
differential inputs, or seven pseudo differential inputs.
3.
1 MSPS serial interface. SPI-/QSPITM-/DSP-/MICROWIRETM-
compatible interface.
4.
Low power, 29 mW, at a maximum throughput rate of
1 MSPS.
5.
Channel sequencer.
Table 1. Similar Product Selection
Device
Number
Throughput
Rate
Number of bits
Number of
Channels
AD7329
250 kSPS
12-bit plus sign
8
AD7327
500 kSPS
12-bit plus sign
8
AD7324
1000 kSPS
12-bit plus sign
4
AD7323
500 kSPS
12-bit plus sign
4
AD7322
1000 kSPS
12-bit plus sign
2
AD7321
500 kSPS
12-bit plus sign
2
1
Protected by U.S. Patent No. 6,731,232.
AD7328
Rev. 0 | Page 2 of 36
TABLE OF CONTENTS
Features .............................................................................................. 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 7
Absolute Maximum Ratings............................................................ 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Typical Performance Characteristics ........................................... 10
Terminology .................................................................................... 14
Theory of Operation ...................................................................... 16
Circuit Information.................................................................... 16
Converter Operation.................................................................. 16
Analog Input Structure.............................................................. 17
Typical Connection Diagram ................................................... 19
Analog Input ............................................................................... 19
Driver Amplifier Choice............................................................ 21
Registers ........................................................................................... 22
Addressing Registers .................................................................. 22
Control Register ......................................................................... 23
Sequence Register....................................................................... 25
The Range Registers................................................................... 25
Sequencer Operation ..................................................................... 26
Reference ..................................................................................... 28
V
DRIVE
............................................................................................ 28
Temperature Indicator............................................................... 28
Modes of Operation ....................................................................... 29
Normal Mode.............................................................................. 29
Full Shutdown Mode.................................................................. 29
Autoshutdown Mode ................................................................. 30
Autostandby Mode..................................................................... 30
Power vs. Throughput Rate....................................................... 31
Serial Interface ................................................................................ 32
Microprocessor Interfacing........................................................... 33
AD7328 to ADSP-21xx.............................................................. 33
AD7328 to ADSP-BF53x ........................................................... 33
Application Hints ........................................................................... 34
Layout and Grounding .............................................................. 34
Outline Dimensions ....................................................................... 35
Ordering Guide .......................................................................... 35
REVISION HISTORY
10/05--Revision 0: Initial Version
AD7328
Rev. 0 | Page 3 of 36
SPECIFICATIONS
Unless otherwise noted, V
DD
= 12 V to 16.5 V, V
SS
= -12 V to -16.5 V, V
CC
= 4.75 V to 5.25 V, V
DRIVE
= 2.7 V to 5.25 V, V
REF
= 2.5 V to 3.0 V
internal/external, f
SCLK
= 20 MHz, f
S
= 1 MSPS, T
A
= T
MAX
to T
MIN
. With V
CC
< 4.75 V, all specifications are typical.
Table 2.
B
Version
Parameter
1
Min Typ Max Unit
Test
Conditions/Comments
DYNAMIC
PERFORMANCE
F
IN
= 50 kHz sine wave
Signal-to-Noise Ratio (SNR)
2
76
dB
Differential mode
73
dB
Single-ended/pseudo differential mode; 10 V and
5 V ranges
72.5
dB
Single-ended/pseudo differential mode ; 0 V to 10 V
and 2.5 V ranges
Signal-to-Noise + Distortion
(SINAD)
2
75
dB
Differential mode; 2.5 V and 5 V ranges
76
dB
Differential mode; 0 V to 10 V and 10 V ranges
72.5
dB
Single-ended/pseudo differential mode; 2.5 V and
5 V ranges
72.5
dB
Single-ended/pseudo differential mode; 0 V to 10 V
and 10 V ranges
Total Harmonic Distortion (THD)
2
-80
dB
Differential mode; 2.5 V and 5 V ranges
-82
dB
Differential mode; 0 V to 10 V and 10 V ranges
-77.5
dB
Single-ended/pseudo differential mode; 2.5 V and
5 V ranges
-80
dB
Single-ended/pseudo differential mode; 0 V to 10 V
and 10 V ranges
Peak Harmonic or Spurious Noise
(SFDR)
2
-80
dB
Differential mode; 2.5 V and 5 V ranges
-82
dB
Differential mode; 0 V to 10 V and 10 V ranges
-78.5
dB
Single-ended/pseudo differential mode; 2.5 V and 5 V
ranges
-79
dB
Single-ended/pseudo differential mode; 0 V to 10 V
and 10 V ranges
Intermodulation Distortion (IMD)
2
fa = 50 kHz, fb = 30 kHz
Second-Order Terms
-88
dB
Third-Order Terms
-90
dB
Aperture Delay
3
7
ns
Aperture Jitter
3
50
ps
Common-Mode Rejection
(CMRR)
2
-79
dB
Up to 100 kHz ripple frequency; see Figure 17
Channel-to-Channel Isolation
2
-72
dB
F
IN
on unselected channels up to 100 kHz; see Figure 14
Full Power Bandwidth
22
MHz
At 3 dB
5
MHz
At 0.1 dB
AD7328
Rev. 0 | Page 4 of 36
B
Version
Parameter
1
Min Typ Max Unit
Test
Conditions/Comments
DC ACCURACY
4
All dc accuracy specifications are typical for 0 V to
10 V mode.
Resolution 13
Bits
No Missing Codes
12-bit
plus sign
Bits
Differential
mode
11-bit
plus sign
Bits
Single-ended/pseudo differential mode
Integral Nonlinearity
2
1.1
LSB
Differential
mode
1
LSB
Single-ended/pseudo differential mode
-0.7/+1.2
LSB
Single-ended/pseudo differential mode
(LSB = FSR/8192)
Differential Nonlinearity
2
-0.9/+1.5
LSB
Differential mode; guaranteed no missing codes to
13 bits
0.9
LSB
Single-ended mode; guaranteed no missing codes to
12 bits
-0.7/+1
LSB
Single-ended/psuedo differential mode
(LSB = FSR/8192)
Offset Error
2, 5
-4/+9
LSB
Single-ended/pseudo differential mode
7
LSB
Differential mode
Offset Error Match
2, 5
0.5
LSB
Single-ended/pseudo differential mode
0.3
LSB
Differential
mode
Gain Error
2, 5
7.5
LSB
Single-ended/pseudo differential mode
14
LSB
Differential mode
Gain Error Match
2, 5
0.35
LSB
Single-ended/pseudo differential mode
0.3
LSB
Differential
mode
Positive Full-Scale Error
2, 6
4
LSB
Single-ended/pseudo differential mode
7
14.5
LSB
Differential mode
Positive Full-Scale Error Match
2, 6
0.2
LSB
Single-ended/pseudo differential mode
0.2
LSB
Differential
mode
Bipolar Zero Error
2, 6
8.5
LSB
Single-ended/pseudo differential mode
7.5
LSB
Differential
mode
Bipolar Zero Error Match
2, 6
0.35
LSB
Single-ended/pseudo differential mode
0.2
LSB
Differential
mode
Negative Full-Scale Error
2, 6
4
LSB
Single-ended/pseudo differential mode
6
14
LSB
Differential mode
Negative Full-Scale Error Match
2, 6
0.2
LSB
Single-ended/pseudo differential mode
0.2
LSB
Differential
mode
AD7328
Rev. 0 | Page 5 of 36
B
Version
Parameter
1
Min Typ Max Unit
Test
Conditions/Comments
ANALOG
INPUT
Input Voltage Ranges
Reference = 2.5 V; see Table 6
(Programmed via Range
Register)
10
V
V
DD
= 10 V min, V
SS
= -10 V min, V
CC
= 2.7 V to 5.25 V
5
V
V
DD
= 5 V min, V
SS
= -5 V min, V
CC
= 2.7 V to 5.25 V
2.5
V
V
DD
= 5 V min, V
SS
= - 5 V min, V
CC
= 2.7 V to 5.25 V
0 to 10
V
V
DD
= 10 V min, V
SS
= AGND min, V
CC
= 2.7 V to 5.25 V
Pseudo Differential V
IN
(-)
Input Range
V
DD
= 16.5 V, V
SS
= -16.5 V, V
CC
= 5 V; see Figure 40 and
Figure 41
3.5
V
Reference = 2.5 V; range = 10 V
6
V
Reference = 2.5 V; range = 5 V
5
V
Reference = 2.5 V; range = 2.5 V
+3/-5
V
Reference = 2.5 V; range = 0 V to 10 V
DC Leakage Current
200
nA
V
IN
= V
DD
or V
SS
Input Capacitance
3
13.5
pF
When in track, 10 V range
16.5
pF
When in track, 5 V and 0 V to 10 V ranges
21.5
pF
When in track, 2.5 V range
3
pF
When in hold, all ranges
REFERENCE
INPUT/OUTPUT
Input Voltage Range
2.5
3
V
Input DC Leakage Current
1
A
Input Capacitance
10
pF
Reference Output Voltage
2.5
V
Reference Output Voltage Error
@ 25C
5
mV
Reference Output Voltage
T
MIN
to T
MAX
10
mV
Reference Temperature
Coefficient
25
ppm/C
6
ppm/C
Reference Output Impedance
7
LOGIC
INPUTS
Input High Voltage, V
INH
2.4
V
Input Low Voltage, V
INL
0.8
V
V
CC
= 4.75 V to 5.25 V
0.4
V
V
CC
= 2.7 to 3.6 V
Input Current, I
IN
1
A
V
IN
= 0 V or V
DRIVE
Input Capacitance, C
IN
3
10
pF
LOGIC
OUTPUTS
Output High Voltage, V
OH
V
DRIVE
-
0.2 V
V
I
SOURCE
= 200 A
Output Low Voltage, V
OL
0.4
V
I
SINK
= 200 A
Floating-State Leakage Current
1
A
Floating-State Output
Capacitance
3
5
pF
Output Coding
Straight natural binary
Coding bit set to 1 in control register
Twos complement
Coding bit set to 0 in control register
CONVERSION
RATE
Conversion Time
800
ns
16 SCLK cycles with SCLK = 20 MHz
Track-and-Hold Acquisition
Time
2, 3
305
ns
Full-scale step input; see the Terminology section
Throughput Rate
1
MSPS
See the Serial Interface section; V
CC
= 4.75 V to 5.25 V
770
kSPS
V
CC
< 4.75 V
AD7328
Rev. 0 | Page 6 of 36
B
Version
Parameter
1
Min Typ Max Unit
Test
Conditions/Comments
POWER REQUIREMENTS
Digital inputs = 0 V or V
DRIVE
V
DD
12
16.5
V
See
Table 6
V
SS
-12
-16.5
V
See
Table 6
V
CC
2.7
5.25
V
See
Table 6; typical specifications for V
CC
< 4.75 V
V
DRIVE
2.7
5.25
V
Normal Mode (Static)
0.9
mA
V
DD
/V
SS
= 16.5 V, V
CC
/V
DRIVE
= 5.25 V
Normal Mode (Operational)
f
SAMPLE
= 1 MSPS
I
DD
360
A
V
DD
= 16.5 V
I
SS
410
A
V
SS
= -16.5 V
I
CC
and I
DRIVE
3.1
mA
V
CC
/V
DRIVE
= 5.25 V
Autostandby Mode (Dynamic)
F
SAMPLE
= 250 kSPS
I
DD
200
A
V
DD
= 16.5 V
I
SS
210
A
V
SS
= -16.5 V
I
CC
and I
DRIVE
1.3
mA
V
CC
/V
DRIVE
= 5.25 V
Autoshutdown Mode (Static)
SCLK on or off
I
DD
1
A
V
DD
= 16.5 V
I
SS
1
A
V
SS
= -16.5 V
I
CC
and I
DRIVE
5.5
A
V
CC
/V
DRIVE
= 5.25 V
Full Shutdown Mode
SCLK on or off
I
DD
1
A
V
DD
= 16.5 V
I
SS
1
A
V
SS
= -16.5 V
I
CC
and I
DRIVE
1
A
V
CC
/V
DRIVE
= 5.25 V
POWER
DISSIPATION
Normal
Mode
29
mW
V
DD
= 16.5 V, V
SS
= -16.5 V, V
CC
= 5.25 V
21
mW
V
DD
= 12 V, V
SS
= -12 V, V
CC
= 5 V
Full Shutdown Mode
38.25
W
V
DD
= 16.5 V, V
SS
= -16.5 V, V
CC
= 5.25 V
1
Temperature ranges is -40C to +85C.
2
See the Terminology section.
3
Sample tested during initial release to ensure compliance.
4
For dc accuracy specifications, the LSB size for differential mode is FSR/8192. For single-ended mode/pseudo differential mode, the LSB size is FSR/4096, unless
otherwise noted.
5
Unipolar 0 V to 10 V range with straight binary output coding.
6
Bipolar range with twos complement output coding.
AD7328
Rev. 0 | Page 7 of 36
TIMING SPECIFICATIONS
V
DD
= 12 V to 16.5 V, V
SS
= -12 V to -16.5 V, V
CC
= 2.7 V to 5.25 V, V
DRIVE
= 2.7 V to 5.25, V
REF
= 2.5 V to 3.0 V internal/external,
T
A
= T
MAX
to T
MIN
. Timing specifications apply with a 32 pF load, unless otherwise noted.
1
Table 3.
Limit
at
T
MIN
, T
MAX
Description
Parameter
V
CC
< 4.75 V
V
CC
= 4.75 V to 5.25 V
Unit
V
DRIVE
V
CC
f
SCLK
50 50
kHz
min
14 20
MHz
max
t
CONVERT
16 t
SCLK
16 t
SCLK
ns max
t
SCLK
= 1/f
SCLK
t
QUIET
75 60
ns
min
Minimum time between end of serial read and next falling edge of CS
t
1
12
5
ns min
Minimum CS pulse width
t
2
2
25 20
ns
min
CS to SCLK set-up time; bipolar input ranges (10 V, 5 V, 2.5 V)
45
35
ns min
Unipolar input range (0 V to 10 V)
t
3
26 14
ns
max
Delay from CS until DOUT three-state disabled
t
4
57
43
ns max
Data access time after SCLK falling edge
t
5
0.4 t
SCLK
0.4 t
SCLK
ns min
SCLK low pulse width
t
6
0.4 t
SCLK
0.4 t
SCLK
ns min
SCLK high pulse width
t
7
13
8
ns min
SCLK to data valid hold time
t
8
40
22
ns max
SCLK falling edge to DOUT high impedance
10
9
ns min
SCLK falling edge to DOUT high impedance
t
9
4
4
ns min
DIN set-up time prior to SCLK falling edge
t
10
2
2
ns min
DIN hold time after SCLK falling edge
t
POWER-UP
750
750
ns max
Power-up from autostandby
500 500
s
max
Power-up from full shutdown/autoshutdown mode, internal reference
25
25
s typ
Power-up from full shutdown/autoshutdown mode, external reference
1
Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
) and timed from a voltage level of 1.6 V.
DRIVE
2
When using the 0 V to 10 V unipolar range, running at 1 MSPS throughput rate with t at 20 ns, the mark space ratio needs to be limited to 50:50.
2
ADD1
1
2
3
4
5
13
14
15
16
WRITE
REG
SEL1
REG
SEL2
LSB
DON'T
CARE
MSB
ADD0
SIGN
DB11
DB10
DB2
DB1
DB0
t
2
t
6
t
4
t
9
t
10
t
3
t
7
t
5
t
8
t
1
t
QUIET
t
CONVERT
SCLK
CS
DOUT
THREE-
STATE
THREE-STATE
DIN
ADD2
3 IDENTIFICATION BITS
04
85
2-
00
2
Figure 2. Serial Interface Timing Diagram
AD7328
Rev. 0 | Page 8 of 36
ABSOLUTE MAXIMUM RATINGS
T
A
= 25C, unless otherwise noted
Table 4.
Parameter Rating
V
DD
to AGND, DGND
-0.3 V to +16.5 V
V
SS
to AGND, DGND
+0.3 V to -16.5 V
V
DD
to Vcc
Vcc - 0.3 V to 16.5 V
V
CC
to AGND, DGND
-0.3 V to +7 V
V
DRIVE
to AGND, DGND
-0.3 V to +7 V
AGND to DGND
-0.3 V to +0.3 V
Analog Input Voltage to AGND
1
V
SS
- 0.3 V to V
DD
+ 0.3 V
Digital Input Voltage to DGND
-0.3 V to +7 V
Digital Output Voltage to GND
-0.3 V to V
DRIVE
+ 0.3 V
REFIN to AGND
-0.3 V to V
CC
+ 0.3 V
Input Current to any Pin
Except Supplies
2
10 mA
Operating Temperature Range
-40C to +85C
Storage Temperature Range
-65C to +150C
Junction Temperature
150C
TSSOP Package
JA
Thermal Impedance
143C/W
JC
Thermal Impedance
45C/W
Pb-free Temperature, Soldering
Reflow 260(0)C
ESD 2.5
kV
1
If the analog inputs are driven from alternative VDD and VSS supply circuitry,
Schottky diodes should be placed in series with the AD7328's VDD and VSS
supplies.
2
Transient currents of up to 100 mA do not cause SCR latch-up.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
AD7328
Rev. 0 | Page 9 of 36
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
DIN
DGND
AGND
V
IN
0
V
SS
REFIN/OUT
CS
DGND
DOUT
V
DRIVE
V
IN
2
V
DD
V
CC
V
IN
5
V
IN
4
V
IN
1
V
IN
7
V
IN
6
V
IN
3
SCLK
AD7328
TOP VIEW
(Not to Scale)
04
852
-
00
3
Figure 3. TSSOP Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
CS
Chip Select. Active low logic input. This input provides the dual function of initiating conversions on
the AD7328 and frames the serial data transfer.
2 DIN
Data In. Data to be written to the on-chip registers is provided on this input and is clocked into the
register on the falling edge of SCLK. See the Registers section.
3, 19
DGND
Digital Ground. Ground reference point for all digital circuitry on the AD7328. The DGND and AGND
voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a
transient basis.
4 AGND
Analog Ground. Ground reference point for all analog circuitry on the AD7328. All analog input signals
and any external reference signal should be referred to this AGND voltage. The AGND and DGND voltages
should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis.
5 REFIN/OUT
Reference Input/Reference Output. The on-chip reference is available on this pin for use external to the
AD7328. Alternatively, the internal reference can be disabled and an external reference applied to this
input. On power-up, the external reference mode is the default condition. The nominal internal reference
voltage is 2.5 V, which appears at the pin. A 680 nF capacitor should be placed on the reference pin
(see the Reference section).
6 V
SS
Negative Power Supply Voltage. This is the negative supply voltage for the analog input section.
7, 8, 14, 13, 9, 10,
12, 11
V
IN
0 to V
IN
7
Analog Input 0 to Analog Input 7. The analog inputs are multiplexed into the on-chip track-and-hold.
The analog input channel for conversion is selected by programming the Channel Address Bit ADD2
through Bit ADD0 in the control register. The inputs can be configured as eight single-ended inputs,
four true differential input pairs, four pseudo differential inputs, or seven pseudo differential inputs.
The configuration of the analog inputs is selected by programming the mode bits, Bit Mode 1 and
Bit Mode 0, in the control register. The input range on each input channel is controlled by program-
ming the range registers. Input ranges of 10 V, 5 V, 2.5 V, and 0 V to 10 V can be selected on each
analog input channel when a 2.5 V reference voltage is used (see the Registers section).
15 V
DD
Positive Power Supply Voltage. This is the positive supply voltage for the analog input section.
16 V
CC
Analog Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for the ADC core on the AD7328.
This supply should be decoupled to AGND. Specifications apply from V
CC
= 4.75 V to 5.25 V.
17 V
DRIVE
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface
operates. This pin should be decoupled to DGND. The voltage at this pin may be different to that at V
CC
,
but it should not exceed V
CC
by more than 0.3 V.
18 DOUT
Serial Data Output. The conversion output data is supplied to this pin as a serial data stream. The bits
are clocked out on the falling edge of the SCLK input, and 16 SCLKs are required to access the data. The
data stream consists of three channel identification bits, the sign bit, and 12 bits of conversion data.
The data is provided MSB first. See the Serial Interface section.
20 SCLK
Serial Clock, Logic Input. A serial clock input provides the SCLK used for accessing the data from the
AD7328. This clock is also used as the clock source for the conversion process.
AD7328
Rev. 0 | Page 10 of 36
TYPICAL PERFORMANCE CHARACTERISTICS
0
140
0
500
FREQUENCY (kHz)
S
N
R (
d
B)
20
40
60
80
100
120
50
100
150
200
250
300
350
400
450
4096 POINT FFT
V
CC
= V
DRIVE
= 5V
V
DD
, V
SS
= 15V
T
A
= 25C
INT/EXT 2.5V REFERENCE
10V RANGE
F
IN
= 50kHz
SNR = 77.30dB
SINAD = 76.85dB
THD = 86.96dB
SFDR = 88.22dB
0
485
2-
0
04
Figure 4. FFT True Differential Mode
0
140
0
500
FREQUENCY (kHz)
S
N
R (
d
B)
20
40
60
80
100
120
50
100
150
200
250
300
350
400
450
4096 POINT FFT
V
CC
= V
DRIVE
= 5V
V
DD
, V
SS
= 15V
T
A
= 25C
INT/EXT 2.5V REFERENCE
10V RANGE
F
IN
= 50kHz
SNR = 74.67dB
SINAD = 74.03dB
THD = 82.68dB
SFDR = 85.40dB
0
485
2-
0
05
Figure 5. FFT Single-Ended Mode
1.0
1.0
0
8192
CODE
DN
L ERR
O
R (
L
SB)
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
0.8
1024
2048
3072
4096
5120
6144
7168
512
1536
2560
3584
4608
5632
6656
7680
V
CC
= V
DRIVE
= 5V
T
A
= 25C
V
DD
, V
SS
= 15V
INT/EXT 2.5V REFERENCE
10V RANGE
+DNL = +0.72LSB
DNL = 0.22LSB
0
485
2-
00
6
Figure 6. Typical DNL True Differential Mode
1.0
1.0
0
8192
CODE
I
NL
E
R
RO
R (
L
S
B)
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
0.8
1024
2048
3072
4096
5120
6144
7168
512
1536
2560
3584
4608
5632
6656
7680
048
52
-
0
07
V
CC
= V
DRIVE
= 5V
T
A
= 25C
V
DD
, V
SS
= 15V
INT/EXT 2.5V REFERENCE
10V RANGE
+INL = +0.55LSB
INL = 0.68LSB
Figure 7. Typical INL True Differential Mode
1.0
1.0
0
8192
CODE
DN
L ERR
O
R (
L
SB)
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
0.8
1024
2048
3072
4096
5120
6144
7168
512
1536
2560
3584
4608
5632
6656
7680
V
CC
= V
DRIVE
= 5V
T
A
= 25C
V
DD
, V
SS
= 15V
INT/EXT 2.5V REFERENCE
0
485
2-
04
3
10V RANGE
+DNL = +0.79LSB
DNL = 0.38LSB
Figure 8. Typical DNL Single-Ended Mode
1.0
1.0
0
8192
CODE
IN
L
E
R
R
O
R
(
L
S
B
)
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
0.8
1024
2048
3072
4096
5120
6144
7168
512
1536
2560
3584
4608
5632
6656
7680
V
CC
= V
DRIVE
= 5V
T
A
= 25C
V
DD
, V
SS
= 15V
INT/EXT 2.5V REFERENCE
10V RANGE
+INL = +0.87LSB
INL = 0.49LSB
0
485
2-
04
4
Figure 9. Typical INL Single-Ended Mode
AD7328
Rev. 0 | Page 11 of 36
50
100
10
1000
ANALOG INPUT FREQUENCY (kHz)
T
HD (
d
B)
100
55
60
65
70
75
80
85
90
95
2.5V SE
2.5V DIFF
5V DIFF
5V SE
10V SE
10V DIFF
0V TO +10V SE
V
CC
= 5V
V
DD
/V
SS
= 12V
T
A
= 25C
f
S
= 1MSPS
0V TO +10V DIFF
0
485
2-
0
08
Figure 10. THD vs. Analog Input Frequency for Single-Ended (SE) and True
Differential Mode (Diff) at 5 V V
CC
50
100
10
1000
ANALOG INPUT FREQUENCY (kHz)
T
HD (
d
B)
100
55
60
65
70
75
80
85
90
95
V
CC
= 3V
V
DD
/V
SS
= 12V
T
A
= 25C
f
S
= 1MSPS
2.5V SE
2.5V DIFF
5V DIFF
5V SE
10V DIFF
0V TO +10V SE
10V SE
0V TO +10V DIFF
0
485
2-
0
09
Figure 11. THD vs. Analog Input Frequency for Single-Ended (SE) and True
Differential Mode (Diff) at 3 V V
CC
80
50
10
1000
ANALOG INPUT FREQUENCY (kHz)
S
I
NAD (
d
B)
100
75
70
65
60
55
V
CC
= 5V
V
DD
/V
SS
= 12V
T
A
= 25C
f
S
= 1MSPS
2.5V SE
2.5V DIFF
5V DIFF
10V DIFF
5V SE
0V TO +10V SE
10V SE
0V TO +10V DIFF
0
485
2-
0
10
Figure 12. SINAD vs. Analog Input Frequency for Single-Ended (SE) and
Differential Mode (Diff) at 5 V V
CC
80
50
10
1000
ANALOG INPUT FREQUENCY (kHz)
S
I
NAD (
d
B)
100
75
70
65
60
55
V
CC
= 3V
V
DD
/V
SS
= 12V
T
A
= 25C
f
S
= 1MSPS
2.5V SE
2.5V DIFF
5V DIFF
10V DIFF
0V TO +10V SE
10V SE
5V SE
0V TO +10V DIFF
0
485
2-
0
1
1
Figure 13. SINAD vs. Analog Input Frequency for Single-Ended (SE) and
Differential Mode (Diff) at 3 V V
CC
50
95
0
600
04
85
2
-
0
1
2
FREQUENCY OF INPUT NOISE (kHz)
CHANNE
L
-
T
O
-
CHANNE
L
I
S
O
L
A
T
I
O
N (
d
B) 55
60
65
70
75
80
85
90
100
200
300
400
500
V
DD
/V
SS
= 12V
SINGLE-ENDED MODE
f
S
= 1MSPS
T
A
= 25C
50kHz ON SELECTED CHANNEL
V
CC
= 3V
V
CC
= 5V
Figure 14. Channel-to-Channel Isolation
10k
0
2
CODE
NUM
BE
R O
F
O
CCURRANCE
S
9k
8k
7k
6k
5k
4k
3k
2k
1k
1
0
1
2
0
228
9469
303
0
V
CC
= 5V
V
DD
/V
SS
= 12V
RANGE = 10V
10k SAMPLES
T
A
= 25C
0
485
2-
0
13
Figure 15. Histogram of Codes, True Differential Mode
AD7328
Rev. 0 | Page 12 of 36
8k
0
3
CODE
NUM
BE
R O
F
O
CCURANCE
S
7k
6k
5k
4k
3k
2k
1k
2
1
0
1
2
3
V
CC
= 5V
V
DD
/V
SS
= 12V
RANGE = 10V
10k SAMPLES
T
A
= 25C
0
23
1201
7600
1165
11
0
0
485
2-
0
14
Figure 16. Histogram of Codes, Single-Ended Mode
50
100
0
04
85
2-
0
55
RIPPLE FREQUENCY (kHz)
CM
RR (
d
B)
55
60
65
70
75
80
85
90
95
200
400
600
800
1000
1200
DIFFERENTIAL MODE
F
IN
= 50kHz
V
DD
/V
SS
= 12V
f
S
= 1MSPS
T
A
= 25C
V
CC
= 5V
V
CC
= 3V
Figure 17. CMRR vs. Common-Mode Ripple Frequency
2.0
2.0
V
DD
/V
SS
SUPPLY VOLTAGE (V)
DN
L E
R
RO
R
(
L
S
B
)
1.5
1.0
0.5
0
0.5
1.0
1.5
5
7
9
11
13
15
17
19
0
485
2-
04
9
5V RANGE
V
CC
= V
DRIVE
= 5V
INTERNAL REFERENCE
SINGLE-ENDED MODE
DNL = 750kSPS
DNL = 750kSPS
DNL = 500kSPS
DNL = 500kSPS
DNL = 1MSPS
DNL = 1MSPS
Figure 18. DNL Error vs. Supply Voltage at 500 kSPS, 750 kSPS, and 1 MSPS
2.0
2.0
V
DD
/V
SS
SUPPLY VOLTAGE (V)
IN
L
E
R
R
O
R
(
L
S
B
)
1.5
1.0
0.5
0
0.5
1.0
1.5
5
7
9
11
13
15
17
19
0
485
2-
05
0
5V RANGE
V
CC
= V
DRIVE
= 5V
INTERNAL REFERENCE
SINGLE-ENDED MODE
INL = 750kSPS
INL = 500kSPS
INL = 1MSPS
INL = 750kSPS
INL = 500kSPS
INL = 1MSPS
Figure 19. INL Error vs. Supply Voltage at 500 kSPS, 750 kSPS, and 1 MSPS
50
100
0
1200
04
85
2-
0
54
SUPPLY RIPPLE FREQUENCY (kHz)
P
S
RR (
d
B)
55
60
65
70
75
80
85
90
95
200
400
600
800
1000
100mV p-p SINE WAVE ON EACH SUPPLY
NO DECOUPLING
SINGLE-ENDED MODE
f
S
= 1MSPS
V
CC
= 5V
V
CC
= 3V
V
DD
= 12V
V
SS
= 12V
Figure 20. PSRR vs. Supply Ripple Frequency Without Supply Decoupling
10
1000
ANALOG INPUT FREQUENCY (kHz)
T
HD (
d
B)
100
04
852
-
01
5
50
55
60
65
70
75
80
85
90
95
V
CC
= V
DRIVE
= 5V
V
DD
/V
SS
= 12V
T
A
= 25C
INTERNAL REFERENCE
RANGE = 10V AND 2.5V
R
IN
= 50,
2.5V RANGE
R
IN
= 50,
10V RANGE
R
IN
= 100,
2.5V RANGE
R
IN
= 1000,
2.5V RANGE
R
IN
= 2000,
2.5V RANGE
R
IN
= 4700,
2.5V RANGE
R
IN
= 2000, 10V RANGE
R
IN
= 1000, 10V RANGE
R
IN
= 100, 10V RANGE
Figure 21. THD vs. Analog Input Frequency for Various Source Impedances,
True Differential Mode
AD7328
Rev. 0 | Page 13 of 36
10
1000
INPUT FREQUENCY (kHz)
T
HD (
d
B)
100
04
852
-
01
6
50
55
60
65
70
75
80
85
90
95
V
CC
= V
DRIVE
= 5V
V
DD
/V
SS
= 12V
T
A
= 25C
INTERNAL REFERENCE
RANGE = 10V AND 2.5V
R
IN
= 2000, 10V RANGE
R
IN
= 1000, 10V RANGE
R
IN
= 50,
2.5V RANGE
R
IN
= 100,
10V RANGE
R
IN
= 100,
2.5V RANGE
R
IN
= 1000,
2.5V RANGE
R
IN
= 2000,
2.5V RANGE
R
IN
= 50,
10V RANGE
Figure 22. THD vs. Analog Input Frequency for Various Source Impedances,
Single-Ended Mode
AD7328
Rev. 0 | Page 14 of 36
TERMINOLOGY
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Integral Nonlinearity
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The
endpoints of the transfer function are zero scale (a point 1 LSB
below the first code transition) and full scale (a point 1 LSB above
the last code transition).
Offset Code Error
This applies to straight binary output coding. It is the deviation
of the first code transition (00 . . . 000) to (00 . . . 001) from the
ideal, that is, AGND + 1 LSB.
Offset Error Match
This is the difference in offset error between any two input
channels.
Gain Error
This applies to straight binary output coding. It is the deviation
of the last code transition (111 . . . 110) to (111 . . . 111) from the
ideal (that is, 4 V
REF
- 1 LSB, 2 V
REF
- 1 LSB, V
REF
- 1 LSB)
after adjusting for the offset error.
Gain Error Match
This is the difference in gain error between any two input channels.
Bipolar Zero Code Error
This applies when using twos complement output coding and a
bipolar analog input. It is the deviation of the midscale transition
(all 1s to all 0s) from the ideal input voltage, that is, AGND - 1 LSB.
Bipolar Zero Code Error Match
This refers to the difference in bipolar zero code error between
any two input channels.
Positive Full-Scale Error
This applies when using twos complement output coding and
any of the bipolar analog input ranges. It is the deviation of the
last code transition (011...110) to (011...111) from the ideal
(4 V
REF
- 1 LSB, 2 V
REF
- 1 LSB, V
REF
- 1 LSB) after adjusting
for the bipolar zero code error.
Positive Full-Scale Error Match
This is the difference in positive full-scale error between any
two input channels.
Negative Full-Scale Error
This applies when using twos complement output coding and
any of the bipolar analog input ranges. This is the deviation of
the first code transition (10 ... 000) to (10 ... 001) from the ideal
(that is, -4 V
REF
+ 1 LSB, -2 V
REF
+ 1 LSB, -V
REF
+ 1 LSB)
after adjusting for the bipolar zero code error.
Negative Full-Scale Error Match
This is the difference in negative full-scale error between any
two input channels.
Track-and-Hold Acquisition Time
The track-and-hold amplifier returns into track mode after the
14
th
SCLK rising edge. Track-and-hold acquisition time is the
time required for the output of the track-and-hold amplifier to
reach its final value, within 1/2 LSB, after the end of a conversion.
For the 2.5 V range, the specified acquisition time is the time
required for the track-and-hold amplifier to settle to within 1 LSB.
Signal to (Noise + Distortion) Ratio
This is the measured ratio of signal to (noise + distortion) at
the output of the A/D converter. The signal is the rms amplitude
of the fundamental. Noise is the sum of all nonfundamental
signals up to half the sampling frequency (f
S
/2), excluding dc.
The ratio is dependent on the number of quantization levels in
the digitization process. The more levels, the smaller the quan-
tization noise. Theoretically, the signal to (noise + distortion) ratio
for an ideal N-bit converter with a sine wave input is given by
Signal to (Noise + Distortion) = (6.02 N + 1.76) dB
For a 13-bit converter, this is 80.02 dB.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7328, it is defined as
1
2
6
2
5
2
4
2
3
2
2
log
20
)
dB
(
V
V
V
V
V
V
THD
+
+
+
+
=
where V
1
is the rms amplitude of the fundamental, and V
2
, V
3
,
V
4
, V
5
, and V
6
are the rms amplitudes of the second through the
sixth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to f
S
/2 and excluding dc) to the rms value of
the fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, the
largest harmonic could be a noise peak.
AD7328
Rev. 0 | Page 15 of 36
Channel-to-Channel Isolation
Channel-to-channel isolation is a measure of the level of crosstalk
between any two channels. It is measured by applying a full-scale
100 kHz sine wave signal to all unselected input channels and
determining the degree to which the signal attenuates in the
selected channel with a 50 kHz signal. Figure 14 shows the worst-
case across all eight channels for the AD7328. The analog input
range is programmed to be the same on all channels.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and fb,
any active device with nonlinearities creates distortion products
at sum and difference frequencies of mfa nfb, where m, n = 0,
1, 2, 3, and so on. Intermodulation distortion terms are those
for which neither m nor n are equal to 0. For example, the
second-order terms include (fa + fb) and (fa - fb), whereas the
third-order terms include (2fa + fb), (2fa - fb), (fa + 2fb), and
(fa - 2fb).
The AD7328 is tested using the CCIF standard where two input
frequencies near the top end of the input bandwidth are used.
In this case, the second-order terms are usually distanced in
frequency from the original sine waves, whereas the third-order
terms are usually at a frequency close to the input frequencies.
As a result, the second- and third-order terms are specified
separately. The calculation of the intermodulation distortion is
per the THD specification, where it is the ratio of the rms sum
of the individual distortion products to the rms amplitude of
the sum of the fundamentals expressed in decibels.
PSR (Power Supply Rejection)
Variations in power supply affect the full-scale transition but not
the converter's linearity. Power supply rejection is the maximum
change in the full-scale transition point due to a change in
power supply voltage from the nominal value (see the Typical
Performance Characteristics section).
CMRR (Common-Mode Rejection Ratio)
CMRR is defined as the ratio of the power in the ADC output
at full-scale frequency, f, to the power of a 100 mV sine wave
applied to the common-mode voltage of the VIN+ and VIN-
frequency f
S
as
CMRR (dB) = 10 log (Pf/Pf
S
)
where Pf is the power at frequency f in the ADC output, and Pf
S
is the power at frequency f
S
in the ADC output (see Figure 17).
AD7328
Rev. 0 | Page 16 of 36
THEORY OF OPERATION
CIRCUIT INFORMATION
The AD7328 is a fast, 8-channel, 12-bit plus sign, bipolar input,
serial A/D converter. The AD7328 can accept bipolar input
ranges that include 10 V, 5 V, 2.5 V; it can also accept a 0 V
to 10 V unipolar input range. A different analog input range can
be programmed on each analog input channel via the on-chip
registers. The AD7328 has a high speed serial interface that can
operate at throughput rates up to 1 MSPS.
The AD7328 requires V
DD
and V
SS
dual supplies for the high
voltage analog input structures. These supplies must be equal
to or greater than the analog input range. See Table 6 for the
requirements of these supplies for each analog input range. The
AD7328 requires a low voltage 2.7 V to 5.25 V V
CC
supply to
power the ADC core.
Table 6. Reference and Supply Requirements for Each
Analog Input Range
Selected Analog
Input Range (V)
Reference
Voltage (V)
Full-Scale
Input
Range (V)
AV
CC
(V)
Minimum
V
DD
/V
SS
(V)
2.5 10
3/5
10
10
3.0 12
3/5
12
2.5 5
3/5
5
5
3.0 6
3/5
6
2.5 2.5
3/5
5
2.5
3.0 3
3/5
5
2.5
0 to +10
3/5
+10/AGND
0 to 10
3.0
0 to +12
3/5
+12/AGND
To meet the specified performance when the AD7328 is
configured with the minimum V
DD
and V
SS
supplies for a
chosen analog input range, the throughput rate should be
decreased from the maximum throughput range (see the
Typical Performance Characteristics section). Figure 18 and
Figure 19 show the change in INL and DNL as the V
DD
and V
SS
voltages are varied. When operating at the maximum through-
put rate, as the V
DD
and V
SS
supply voltages are reduced, the INL
and DNL error increases. However, as the throughput rate is
reduced with the minimum V
DD
and V
SS
supplies, the INL and
DNL error is reduced.
Figure 31 shows the change in THD as the V
DD
and V
SS
supplies
are reduced. At the maximum throughput rate, the THD
degrades as V
DD
and V
SS
are reduced. Again, as the throughput
rate is reduced with the minimum V
DD
and V
SS
supplies, the
THD degradation is greatly reduced. The degradation is due to
an increase in the on-resistance of the input multiplexer when
the V
DD
and V
SS
supplies are reduced.
The analog inputs can be configured as eight single-ended
inputs, four true differential inputs, four pseudo differential
inputs, or seven pseudo differential inputs. Selection can be
made by programming the mode bits, Mode 0 and Mode 1, in
the control register.
The serial clock input accesses data from the part and provides
the clock source for each successive approximation ADC. The
AD7328 has an on-chip 2.5 V reference. However, the AD7328
can also work with an external reference. On power-up, the
external reference operation is the default option. If the internal
reference is the preferred option, the user must write to the
reference bit in the control register to select the internal reference
operation.
The AD7328 also features power-down options to allow power
saving between conversions. The power-down modes are selected
by programming the on-chip control register as described in the
Modes of Operation section.
CONVERTER OPERATION
The AD7328 is a successive approximation analog-to-digital
converter built around two capacitive DACs. Figure 23 and
Figure 24 show simplified schematics of the ADC in single-
ended mode during the acquisition and conversion phases,
respectively. Figure 25 and Figure 26 show simplified schematics
of the ADC in differential mode during acquisition and conversion
phases, respectively.
The ADC is composed of control logic, a SAR, and capacitive
DACs. In Figure 23 (the acquisition phase), SW2 is closed and
SW1 is in Position A, the comparator is held in a balanced con-
dition, and the sampling capacitor array acquires the signal on
the input.
CAPACITIVE
DAC
CONTROL
LOGIC
COMPARATOR
AGND
SW2
SW1
A
B
C
S
V
IN
0
04
852
-
0
17
Figure 23. ADC Acquisition Phase (Single-Ended)
When the ADC starts a conversion (Figure 24), SW2 opens and
SW1 moves to Position B, causing the comparator to become
unbalanced. The control logic and the charge redistribution
DAC are used to add and subtract fixed amounts of charge from
the capacitive DAC to bring the comparator back into a balanced
condition. When the comparator is rebalanced, the conversion
is complete. The control logic generates the ADC output code.
AD7328
Rev. 0 | Page 17 of 36
CAPACITIVE
DAC
CONTROL
LOGIC
COMPARATOR
AGND
SW2
SW1
A
B
C
S
V
IN
0
04
852
-
018
Figure 24. ADC Conversion Phase (Single-Ended)
Figure 25 shows the differential configuration during the ac-
quisition phase. For the conversion phase, SW3 opens and SW1
and SW2 move to Position B (Figure 26). The output impedances
of the source driving the V
IN
+ and V
IN
- pins must be matched;
otherwise, the two inputs will have different settling times, resulting
in errors.
CAPACITIVE
DAC
CONTROL
LOGIC
CAPACITIVE
DAC
COMPARATOR
SW3
SW1
A
B
C
S
C
S
V
IN
+
SW2
A
B
V
IN
V
REF
04
852
-
019
Figure 25. ADC Differential Configuration During Acquisition Phase
CAPACITIVE
DAC
CONTROL
LOGIC
CAPACITIVE
DAC
COMPARATOR
SW3
SW1
A
B
C
S
C
S
V
IN
+
SW2
A
B
V
IN
V
REF
04
852
-
020
Figure 26. ADC Differential Configuration During Conversion Phase
Output Coding
The AD7328 default output coding is set to twos complement.
The output coding is controlled by the coding bit in the control
register. To change the output coding to straight binary coding,
the coding bit in the control register must be set. When operating
in sequence mode, the output coding for each channel in the
sequence is the value written to the coding bit during the last
write to the control register.
Transfer Functions
The designed code transitions occur at successive integer
LSB values (that is, 1 LSB, 2 LSB, and so on). The LSB size
is dependent on the analog input range selected.
Table 7. LSB Sizes for Each Analog Input Range
Input Range
Full-Scale Range/8192 Codes
LSB Size
10 V
20 V
2.441 mV
5 V
10 V
1.22 mV
2.5 V
5 V
0.61 mV
0 V to 10 V
10 V
1.22 mV
The ideal transfer characteristic for the AD7328 when twos
complement coding is selected is shown in Figure 27. The ideal
transfer characteristic for the AD7328 when straight binary coding
is selected is shown in Figure 28.
011...111
011...110
000...001
000...000
111...111
FSR/2 + 1LSB
AGND + 1LSB
+FSR/2 1LSB BIPOLAR RANGES
+FSR 1LSB
UNIPOLAR RANGE
AGND 1LSB
ANALOG INPUT
A
D
C CO
DE
100...010
100...001
100...000
0
4852
-
02
1
Figure 27. Twos Complement Transfer Characteristic (Bipolar Ranges)
111...111
111...110
111...000
011...111
FSR/2 + 1LSB
AGND + 1LSB
+FSR/2 1LSB BIPOLAR RANGES
+FSR 1LSB
UNIPOLAR RANGE
ANALOG INPUT
ADC
CO
DE
000...010
000...001
000...000
0485
2-
02
2
Figure 28. Straight Binary Transfer Characteristic (Bipolar Ranges)
ANALOG INPUT STRUCTURE
The analog inputs of the AD7328 can be configured as single-
ended, true differential, or pseudo differential via the control
register mode bits (see Table 10). The AD7328 can accept true
bipolar input signals. On power-up, the analog inputs operate as
eight single-ended analog input channels. If true differential or
pseudo differential is required, a write to the control register is
necessary after power-up to change this configuration.
Figure 29 shows the equivalent analog input circuit of the
AD7328 in single-ended mode. Figure 30 shows the equivalent
analog input structure in differential mode. The two diodes
provide ESD protection for the analog inputs.
D
D
V
DD
C2
R1
V
IN
0
V
SS
C1
04
852
-
02
3
Figure 29. Equivalent Analog Input Circuit (Single-Ended)
AD7328
Rev. 0 | Page 18 of 36
D
D
V
DD
C2
R1
V
IN
+
V
SS
C1
D
D
V
DD
C2
R1
V
IN
V
SS
C1
0
485
2-
0
24
Figure 30. Equivalent Analog Input Circuit (Differential)
Care should be taken to ensure that the analog input does
not exceed the V
DD
and V
SS
supply rails by more than 300 mV.
Exceeding this value causes the diodes to become forward
biased and to start conducting into either the V
DD
supply rail
or V
SS
supply rail. These diodes can conduct up to 10 mA
without causing irreversible damage to the part.
In Figure 29 and Figure 30, Capacitor C1 is typically 4 pF and
can primarily be attributed to pin capacitance. Resistor R1 is a
lumped component made up of the on-resistance of the input
multiplexer and the track-and-hold switch. Capacitor C2 is the
sampling capacitor; its capacitance varies depending on the
analog input range selected (see the Specifications section).
Track-and-Hold Section
The track-and-hold of the analog input on the AD7328 allows
the ADC to accurately convert an input sine wave of full-scale
amplitude to 13-bit accuracy. The input bandwidth of the track-
and-hold is greater than the Nyquist rate of the ADC. The AD7328
can handle frequencies up to 22 MHz.
The track-and-hold enters its tracking mode on the 14
th
SCLK
rising edge after the CS falling edge. The time required to acquire
an input signal depends on how quickly the sampling capacitor
is charged. With 0 source impedance, 305 ns is the maximum time
required to acquire the signal to the 13-bit level. The acquisition
time for the 10 V, 5 V, and 0 V to +10 V ranges to settle to
within LSB is typically 200 ns.
The acquisition time required is calculated using the following
formula:
t
ACQ
= 10 ((R
SOURCE
+ R) C)
where C is the sampling capacitance, and R is the resistance
seen by the track-and-hold amplifier looking back on the input.
For the AD7328, the value of R includes the on-resistance of the
input multiplexer and is typically 300 . R
SOURCE
should include
any extra source impedance on the analog input.
The AD7328 enters track mode on the 14
th
SCLK rising edge.
When running the AD7328 at a throughput rate of 1 MSPS with
a 20 MHz SCLK signal, the ADC has approximately
1.5 SCLK + t
8
+ t
QUIET
to acquire the analog input signal. The ADC goes back into
hold mode on the CS falling edge.
As the V
DD
/V
SS
supply voltage is reduced, the on-resistance of
the input multiplexer increases. Therefore, based on the equation
for t
ACQ
, it is necessary to increase the acquisition time provided
to the AD7328 and hence decrease the overall throughput rate.
Figure 31 shows that if the throughput rate is reduced when
operating with minimum V
DD
and V
SS
supplies, the specified
THD performance is maintained.
50
95
5
19
04
852
-
051
V
DD
/V
SS
SUPPLIES (V)
TH
D
(
dB
)
55
60
65
70
75
80
85
90
7
9
11
13
15
17
500kSPS
750kSPS
1MSPS
V
CC
= V
DRIVE
= 5V
INTERNAL REFERENCE
T
A
= 25C
F
IN
= 10kHz
5V RANGE
SE MODE
Figure 31. THD vs. V
DD
/V
SS
Supply Voltage at 500 kSPS, 750 kSPS, and 1 MSPS
Unlike other bipolar ADCs, the AD7328 does not have a
resistive analog input structure. On the AD7328, the bipolar
analog signal is sampled directly onto the sampling capacitor.
This gives the AD7328 high analog input impedance. The
analog input impedance can be calculated from the following
formula:
Z = 1/(f
S
C
S
)
where f
S
is the sampling frequency, and C
S
is the sampling
capacitor value.
C
S
depends on the analog input range chosen (see the
Specifications section). When operating at 1 MSPS, the analog
input impedance is typically 75 k for the 10 V range. As the
sampling frequency is reduced, the analog input impedance
further increases. As the analog input impedance increases, the
current required to drive the analog input therefore decreases.
AD7328
Rev. 0 | Page 19 of 36
TYPICAL CONNECTION DIAGRAM
Figure 32 shows a typical connection diagram for the AD7328.
In this configuration, the AGND pin is connected to the analog
ground plane of the system, and the DGND pin is connected to
the digital ground plane of the system. The analog inputs on the
AD7328 can be configured to operate in single-ended, true dif-
ferential, or pseudo differential mode. The AD7328 can operate
with either an internal or external reference. In Figure 32, the
AD7328 is configured to operate with the internal 2.5 V reference.
A 680 nF decoupling capacitor is required when operating with
the internal reference.
The V
CC
pin can be connected to either a 3 V supply voltage or a
5 V supply voltage. The V
DD
and V
SS
are the dual supplies for the
high voltage analog input structures. The voltage on these pins
must be equal to or greater than the highest analog input range
selected on the analog input channels (see Table 6). The V
DRIVE
pin is connected to the supply voltage of the microprocessor.
The voltage applied to the V
DRIVE
input controls the voltage of
the serial interface. V
DRIVE
can be set to 3 V or 5 V.
AD7328
V
CC
V
DD
1
SERIAL
INTERFACE
C/P
V
IN
0
V
IN
1
V
IN
2
V
IN
3
V
IN
4
V
IN
5
V
IN
6
V
IN
7
REFIN/OUT
CS
DOUT
V
DRIVE
SCLK
DIN
DGND
10F
0.1F
+
10F
0.1F
+
10F
0.1F
+
ANALOG INPUTS
10V, 5V, 2.5V
0V TO +10V
+15V
15V
680nF
V
SS
1
V
CC
+2.7V TO +5.25V
1
MINIMUM V
DD
AND V
SS
SUPPLY VOLTAGES
DEPEND ON THE HIGHEST ANALOG INPUT
RANGE SELECTED.
AGND
04
85
2
-
02
5
10F
0.1F
+
+3V SUPPLY
Figure 32. Typical Connection Diagram
ANALOG INPUT
Single-Ended Inputs
The AD7328 has a total of eight analog inputs when operating
in single-ended mode. Each analog input can be independently
programmed to one of the four analog input ranges. In applications
where the signal source is high impedance, it is recommended
to buffer the signal before applying it to the ADC analog inputs.
Figure 33 shows the configuration of the AD7328 in single-
ended mode.
AD7328
1
V
IN
+
V+
V
V
DD
V
SS
V
CC
5V
AGND
1
ADDITIONAL PINS OMITTED FOR CLARITY.
04
85
2
-
02
6
Figure 33. Single-Ended Mode Typical Connection Diagram
True Differential Mode
The AD7328 can have a total of four true differential analog
input pairs. Differential signals have some benefits over single-
ended signals, including better noise immunity based on the
device's common-mode rejection and improvements in distortion
performance. Figure 34 defines the configuration of the true
differential analog inputs of the AD7328.
AD7328
1
V
IN
+
V
IN
1
ADDITIONAL PINS OMITTED FOR CLARITY.
0
485
2-
027
Figure 34. True Differential Inputs
The amplitude of the differential signal is the difference
between the signals applied to the V
IN
+ and V
IN
- pins in
each differential pair (V
IN
+ - V
IN
-). V
IN
+ and V
IN
- should
be simultaneously driven by two signals of equal amplitude,
dependent on the input range selected, that are 180 out of
phase. Assuming the 4 V
REF
mode, the amplitude of
the differential signal is -20 V to +20 V p-p (2 4 V
REF
),
regardless of the common mode.
The common mode is the average of the two signals
(V
IN
+ + V
IN
-)/2
and is therefore the voltage on which the two input signals are
centered.
This voltage is set up externally, and its range varies with reference
voltage. As the reference voltage increases, the common-mode
range decreases. When driving the differential inputs with an
amplifier, the actual common-mode range is determined by the
amplifier's output swing. If the differential inputs are not driven
from an amplifier, the common-mode range is determined by
the supply voltage on the V
DD
supply pin and the V
SS
supply pin.
When a conversion takes place, the common mode is rejected,
resulting in a noise-free signal of amplitude -2 (4 V
REF
) to
+2 (4 V
REF
) corresponding to digital codes -4096 to +4095.
AD7328
Rev. 0 | Page 20 of 36
048
52
-
0
45
16.5V V
DD
/V
SS
12V V
DD
/V
SS
5
6
V
CO
M
R
ANG
E
(
V
)
4
3
2
1
0
1
2
3
4
5
V
CC
= 3V
V
REF
= 3V
2.5V
RANGE
10V
RANGE
5V RANGE
2.5V
RANGE
5V RANGE
10V
RANGE
Figure 35. Common-Mode Range for V
CC
= 3 V and REFIN/OUT = 3 V
04
852
-
046
16.5V V
DD
/V
SS
12V V
DD
/V
SS
V
CO
M
R
ANG
E
(
V
)
V
CC
= 5V
V
REF
= 3V
8
4
6
4
2
0
2
2.5V
RANGE
10V
RANGE
5V RANGE
2.5V
RANGE
5V RANGE
10V
RANGE
Figure 36. Common-Mode Range for V
CC
= 5 V and REFIN/OUT = 3 V
6
8
4
2
0
2
4
6
04
852
-
047
16.5V V
DD
/V
SS
12V V
DD
/V
SS
V
CO
M
R
ANG
E
(
V
)
V
CC
= 3V
V
REF
= 2.5V
2.5V
RANGE
10V
RANGE
5V RANGE
2.5V
RANGE
5V RANGE
10V
RANGE
Figure 37. Common-Mode Range for V
CC
= 3 V and REFIN/OUT = 2.5 V
8
8
6
4
2
0
2
4
6
04
852
-
048
16.5V V
DD
/V
SS
12V V
DD
/V
SS
V
CO
M
R
ANG
E
(
V
)
V
CC
= 5V
V
REF
= 2.5V
2.5V
RANGE
10V
RANGE
5V RANGE
2.5V
RANGE
5V RANGE
10V
RANGE
Figure 38. Common-Mode Range for V
CC
= 5 V and REFIN/OUT = 2.5 V
Pseudo Differential Inputs
The AD7328 can have four pseudo differential pairs or seven
pseudo differential inputs referenced to a common V
IN
- pin. The
V
IN
+ inputs are coupled to the signal source and must have an
amplitude within the selected range for that channel as program-
med in the range register. A dc input is applied to the V
IN
- pin.
The voltage applied to this input provides an offset for the
V
IN
+ input from ground or a pseudo ground. Pseudo differential
inputs separate the analog input signal ground from the ADC
ground, allowing cancellation of dc common-mode voltages.
Figure 39 shows the configuration of the AD7328 in pseudo
differential mode.
When a conversion takes place, the pseudo ground corresponds
to Code -4096, and the maximum amplitude corresponds to
Code +4095.
AD7328
1
V
IN
+
V+
V
V
DD
V
SS
V
CC
5V
1
ADDITIONAL PINS OMITTED FOR CLARITY.
V
IN
04
85
2-
02
8
Figure 39. Pseudo Differential Inputs
Figure 40 and Figure 41 show the typical voltage range on the
V
IN
- pin for the different analog input ranges when configured
in the pseudo differential mode.
For example, when the AD7328 is configured to operate in
pseudo differential mode and the 5 V range is selected with
16.5 V V
DD
/V
SS
supplies and 5 V V
CC
, the voltage on the
V
IN
- pin can vary from -6.5 V to +6.5 V.
AD7328
Rev. 0 | Page 21 of 36
048
52
-
0
39
8
8
6
4
2
0
2
4
6
2.5V
RANGE
10V
RANGE
10V
RANGE
5V RANGE
2.5V
RANGE
5V RANGE
0V TO +10V
RANGE
0V TO +10V
RANGE
16.5V V
DD
/V
SS
12V V
DD
/V
SS
V
CC
= 5V
V
REF
= 2.5V
The driver amplifier must be able to settle for a full-scale step
to a 13-bit level, 0.0122%, in less than the specified acquisition
time of the AD7328. An op amp such as the AD8021 meets this
requirement when operating in single-ended mode. The
AD8021
needs an external compensating NPO type of capacitor. The
AD8022
can also be used in high frequency applications where
a dual version is required. For lower frequency applications, op
amps such as the
AD797
,
AD845
, and
AD8610
can be used in
the AD7328 single-ended mode configuration.
Differential operation requires that V
IN
+ and V
IN
- be simulta-
neously driven with two signals of equal amplitude that are 180
out of phase. The common mode must be set up externally to
the AD7328. The common-mode range is determined by the
REFIN/OUT voltage, the V
CC
supply voltage, and the particular
amplifier used to drive the analog inputs. Differential mode with
either an ac input or a dc input provides the best THD performance
over a wide frequency range. Because not all applications have a
signal preconditioned for differential operation, there is often a
need to perform the single-ended-to-differential conversion.
This single-ended-to-differential conversion can be performed
using an op amp pair. Typical connection diagrams for an op
amp pair are shown in Figure 42 and Figure 43. In Figure 42,
the common-mode signal is applied to the noninverting input
of the second amplifier.
Figure 40. Pseudo Input Range with V
CC
= 5 V
048
52
-
0
40
2.5V
RANGE
10V
RANGE
10V
RANGE
5V RANGE
2.5V
RANGE
5V RANGE
0V TO +10V
RANGE
0V TO +10V
RANGE
16.5V V
DD
/V
SS
12V V
DD
/V
SS
4
8
2
0
2
4
6
V
CC
= 3V
V
REF
= 2.5V
V
IN
V+
V
3k
1.5k
1.5k
1.5k
1.5k
10k
20k
V
COM
04
852-
0
29
Figure 41. Pseudo Input Range with V
CC
= 3 V
DRIVER AMPLIFIER CHOICE
In applications where harmonic distortion and signal-to-noise
ratio are critical specifications, the analog input of the AD7328
should be driven from a low impedance source. Large source
impedances significantly affect the ac performance of the ADC
and can necessitate the use of an input buffer amplifier.
When no amplifier is used to drive the analog input, the source
impedance should be limited to low values. The maximum source
impedance depends on the amount of THD that can be tolerated
in the application. The THD increases as the source impedance
increases and performance degrades. Figure 21 and Figure 22
show graphs of the THD vs. the analog input frequency for various
source impedances. Depending on the input range and analog
input configuration selected, the AD7328 can handle source
impedances of up to 4.7 k before the THD starts to degrade.
Figure 42. Single-Ended-to-Differential Configuration with the
AD845
V
IN
V+
V
442
442
442
442
442
100
AD8021
AD8021
442
04
852
-
03
0
Due to the programmable nature of the analog inputs on the
AD7328, the choice of op amp used to drive the inputs is a
function of the particular application and also depends on the
input configuration and the analog input voltage ranges selected.
Figure 43. Single-Ended-to-Differential Configuration with the
AD8021
AD7328
Rev. 0 | Page 22 of 36
REGISTERS
The AD7328 has four programmable registers: the control register, sequence register, Range Register 1, and Range Register 2. These
registers are write-only registers.
ADDRESSING REGISTERS
A serial transfer on the AD7328 consists of 16 SCLK cycles. The 3 MSBs on the DIN line during the 16 SCLK transfer are decoded to
determine which register is addressed. The 3 MSBs consist of the write bit, Register Select 1 bit, and Register Select 2 bit. The register
select bits are used to determine which of the four on-board registers is selected. The write bit determines if the data on the DIN line
following the register select bits loads into the addressed register. If the write bit is 1, the bits load into the register addressed by the
register select bits. If the write bit is 0, the data on the DIN line does not load into any register.
Table 8. Decoding Register Select Bits and Write Bit
Write
Register Select 1
Register Select 2
Comment
0
0
0
Data on the DIN line during this serial transfer is ignored.
1 0
0
This combination selects the control register. The subsequent 12 bits are loaded into
the control register.
1 0
1
This combination selects Range Register 1. The subsequent 8 bits are loaded into
Range Register 1.
1 1
0
This combination selects Range Register 2. The subsequent 8 bits are loaded into
Range Register 2.
1 1
1
This combination selects the sequence register. The subsequent 8 bits are loaded into
the sequence register.
AD7328
Rev. 0 | Page 23 of 36
CONTROL REGISTER
The control register is used to select the analog input, analog input configuration, reference, coding, and power mode. The control register is
a write-only, 12-bit register. Data loaded on the DIN line corresponds to the AD7328 configuration for the next conversion. If the sequence
register is being used, data should be loaded into the control register after the range registers and the sequence register have been initialized.
The bit functions of the control register are shown in Table 9 (the power-up status of all bits is 0).
MSB
LSB
15
14 13 12
11
10
9 8 7
6
5 1
3
2
1
0
Write Register
Select 1
Register
Select 2
ADD2 ADD1 ADD0 Mode
1 Mode
0 PM1 PM0 Coding Ref Seq1 Seq2 Weak/
Three-State
0
Table 9. Control Register Details
Bit Mnemonic Description
12, 11, 10
ADD2, ADD1,
ADD0
These three channel address bits are used to select the analog input channel for the next conversion if the
sequencer is not being used. If the sequencer is being used, the three channel address bits are used to
select the final channel in a consecutive sequence.
9, 8
Mode 1, Mode 0
These two mode bits are used to select the configuration of the eight analog input pins, V
IN
0 to V
IN
7. These
pins are used in conjunction with the channel address bits. On the AD7328, the analog inputs can be configured
as eight single-ended inputs, four fully differential inputs, four pseudo differential inputs, or seven pseudo
differential Inputs (see Table 10).
7, 6
PM1, PM0
Power Management Bits. These two bits are used to select different power mode options on the AD7328
(see Table 11).
5 Coding
This bit is used to select the type of output coding the AD7328 uses for the next conversion result. If
coding = 0, the output coding is twos complement. If coding = 1, the output coding is straight binary. When
operating in sequence mode, the output coding for each channel is the value written to the coding bit
during the last write to the control register.
4 Ref
Reference Bit. This bit is used to enable or disable the internal reference. If Ref = 0, the external reference is
enabled and used for the next conversion, and the internal reference is disabled. If Ref = 1, the internal ref-
erence is used for the next conversion. When operating in sequence mode, the reference used for each
channel is the value written to the Ref bit during the last write to the control register.
3, 2
Seq1/Seq2
The Sequence 1 and Sequence 2 bits are used to control the operation of the sequencer (see Table 12).
1
Weak/Three-State
This bit selects the state of the DOUT line at the end of the current serial transfer. If the bit is set to 1, the
DOUT line is weakly driven to Channel Address Bit ADD2 of the following conversion. If this bit is set to 0,
DOUT returns to three-state at the end of the serial transfer (see the Serial Interface section).
The eight analog input channels can be configured as seven pseudo differential analog inputs, four pseudo differential inputs, four true
differential inputs, or eight single-ended analog inputs.
Table 10. Analog Input Configuration Selection
Mode 1 = 1, Mode 0 = 1
Mode 1 = 1, Mode 0 = 0
Mode 1 = 0, Mode 0 =1
Mode 1 = 0, Mode 0 = 0
Channel Address Bits
7 Pseudo Differential I/Ps
4 Fully Differential I/Ps
4 Pseudo Differential I/Ps
8 Single-Ended I/Ps
ADD2 ADD1
ADD0
V
IN
+ V
IN
- V
IN
+ V
IN
- V
IN
+ V
IN
- V
IN
+ V
IN
-
0 0 0 V
IN
0 V
IN
7 V
IN
0 V
IN
1 V
IN
0 V
IN
1 V
IN
0 AGND
0 0 1 V
IN
1 V
IN
7 V
IN
0 V
IN
1 V
IN
0 V
IN
1 V
IN
1 AGND
0 1 0 V
IN
2 V
IN
7 V
IN
2 V
IN
3 V
IN
2 V
IN
3 V
IN
2 AGND
0 1 1 V
IN
3 V
IN
7 V
IN
2 V
IN
3 V
IN
2 V
IN
3 V
IN
3 AGND
1 0 0 V
IN
4 V
IN
7 V
IN
4 V
IN
5 V
IN
4 V
IN
5 V
IN
4 AGND
1 0 1 V
IN
5 V
IN
7 V
IN
4 V
IN
5 V
IN
4 V
IN
5 V
IN
5 AGND
1 1 0 V
IN
6 V
IN
7 V
IN
6 V
IN
7 V
IN
6 V
IN
7 V
IN
6 AGND
1 1 1 Temperature
indicator V
IN
6 V
IN
7 V
IN
6 V
IN
7 V
IN
7 AGND
AD7328
Rev. 0 | Page 24 of 36
Table 11. Power Mode Selection
PM1 PM0 Description
1 1 Full Shutdown Mode. In this mode, all internal circuitry on the AD7328 is powered down. Information in the control register
is retained when the AD7328 is in full shutdown mode.
1 0 Autoshutdown Mode. The AD7328 enters autoshutdown on the 15
th
SCLK rising edge when the control register is updated.
All internal circuitry is powered down in autoshutdown.
0 1 Autostandby Mode. In this mode, all internal circuitry is powered down, excluding the internal reference. The AD7328 enters
autostandby mode on the 15
th
SCLK rising edge after the control register is updated.
0
0
Normal Mode. All internal circuitry is powered up at all times.
Table 12. Sequencer Selection
Seq1 Seq2 Sequence
Type
0 0 The channel sequencer is not used. The analog channel, selected by programming the ADD2 bit to ADD0 bit in the control
register, selects the next channel for conversion.
0 1 Uses the sequence of channels that were previously programmed in the sequence register for conversion. The AD7328
starts converting on the lowest channel in the sequence. The channels are converted in ascending order. If uninterrupted,
the AD7328 keeps converting the sequence. The range for each channel defaults to the range previously written into the
corresponding range register.
1 0 Used in conjunction with the channel address bits in the control register. This allows continuous conversions on a consecutive
sequence of channels, from Channel 0 up to and including a final channel selected by the channel address bits in the control
register. The range for each channel defaults to the range previously written into the corresponding range register.
1 1 The channel sequencer is not used. The analog channel, selected by programming the ADD2 bit to ADD0 bit in the control
register, selects the next channel for conversion.
AD7328
Rev. 0 | Page 25 of 36
SEQUENCE REGISTER
The sequence register on the AD7328 is an 8-bit, write-only register. Each of the eight analog input channels has one corresponding bit in
the sequence register. To select a channel for inclusion in the sequence, set the corresponding channel bit to 1 in the sequence register.
MSB
LSB
16 15
14
13
12
11
10
9 8 7 6 5
4
3
2
1
Write
Register Select 1
Register Select 2
V
IN
0 V
IN
1 V
IN
2 V
IN
3 V
IN
4 V
IN
5 V
IN
6 V
IN
7 0 0 0 0 0
THE RANGE REGISTERS
The range registers is used to select one analog input range per analog input channel. Range Register 1 is used to set the ranges for Channel 0
to Channel 3. It is an 8-bit, write-only register with two dedicated range bits for each of the analog input channels from Channel 0 to Channel 3.
There are four analog input ranges, 10 V, 5 V, 2.5 V, and 0 V to +10 V. A write to Range Register 1 is selected by setting the write bit to 1
and the range select bits to 0 and 1. After the initial write to Range Register 1 occurs, each time an analog input is selected, the AD7328
automatically configures the analog input to the appropriate range, as indicated by Range Register 1. The 10 V input range is selected by
default on each analog input channel (see Table 13).
MSB
LSB
16
15
14
13
12
11
10
9
8
7
6
5 4 3 2 1
Write
Register Select 1
Register Select 2
V
IN
0A V
IN
0B V
IN
1A V
IN
1B V
IN
2A V
IN
2B V
IN
3A V
IN
3B 0 0 0 0 0
Range Register 2 is used to set the ranges for Channel 4 to Channel 7. It is an 8-bit, write-only register with two dedicated range bits for
each of the analog input channels from Channel 4 to Channel 7. There are four analog input ranges, 10 V, 5 V, 2.5 V, and 0 V to +10 V.
After the initial write to Range Register 2 occurs, each time an analog input is selected, the AD7328 automatically configures the analog
input to the appropriate range, as indicated by Range Register 2. The 10 V input range is selected by default on each analog input channel
(see Table 13).
MSB
LSB
16
15
14
13
12
11
10
9
8
7
6
5 4 3 2 1
Write
Register Select 1
Register Select 2
V
IN
4A V
IN
4B V
IN
5A V
IN
5B V
IN
6A V
IN
6B V
IN
7A V
IN
7B 0 0 0 0 0
Table 13. Range Selection
V
IN
xA V
IN
xB Description
0
0
This combination selects the 10 V input range on V
IN
x.
0
1
This combination selects the 5 V input range on V
IN
x.
1
0
This combination selects the 2.5 V input range on V
IN
x.
1
1
This combination selects the 0 V to +10 V input range on V
IN
x.
AD7328
Rev. 0 | Page 26 of 36
SEQUENCER OPERATION
DIN: WRITE TO RANGE REGISTER 1 TO SELECT THE RANGE
FOR EACH ANALOG INPUT CHANNEL.
DOUT: CONVERSION RESULT FROM CHANNEL 0, 10V
RANGE, SINGLE-ENDED MODE.
CS
DIN: TIE DIN LOW/WRITE BIT = 0TO CONTINUE TO CONVERT
THROUGH THE SEQUENCE OF CHANNELS.
DOUT: CONVERSION RESULT FROM FIRST CHANNEL IN
THE SEQUENCE.
CS
DIN: WRITE TO SEQUENCE REGISTER TO SELECT THE
NEW SEQUENCE.
DOUT: CONVERSION RESULT FROM CHANNEL X IN
THE FIRST SEQUENCE.
CS
DIN: WRITE TO RANGE REGISTER 2 TO SELECT THE RANGE
FOR EACH ANALOG INPUT CHANNEL.
DOUT: CONVERSION RESULT FROM CHANNEL 0,
SINGLE-ENDED MODE, RANGE SELECTED IN
RANGE REGISTER 1.
CS
DIN: WRITE TO CONTROL REGISTER TO START THE
SEQUENCE, Seq1 = 0, Seq2 = 1.
DOUT: CONVERSION RESULT FROM CHANNEL 0,
SINGLE-ENDED MODE, RANGE SELECTED IN
RANGE REGISTER 1.
CS
DIN: WRITE TO SEQUENCE REGISTER TO SELECT THE
ANALOG INPUT CHANNELS TO BE INCLUDED IN
THE SEQUENCE.
DOUT: CONVERSION RESULT FROM CHANNEL 0,
SINGLE-ENDED MODE, RANGE SELECTED IN
RANGE REGISTER 1.
CS
POWER ON
CONTINUOUSLY CONVERT
ON THE SELECTED SEQUENCE
OF CHANNELS.
DIN TIED LOW/WRITE BIT = 0.
SELECTING A NEW SEQUENCE.
DIN: WRITE TO CONTROL
REGISTER TO STOP THE
SEQUENCE, Seq1 = 0, Seq2 = 0.
DOUT: CONVERSION RESULT
FROM CHANNEL IN SEQUENCE.
CS
STOPPING
A SEQUENCE.
0
485
2-
0
31
Figure 44. Programmable Sequence Flowchart
The AD7328 can be configured to automatically cycle through a
number of selected channels using the on-chip sequence register
with the Seq1 bit and the Seq2 bit in the control register. Figure 44
shows how to program the AD7328 register to operate in sequence
mode.
After power-up, all of the four on-chip registers contain default
values. Each analog input has a default input range of 10 V. If
different analog input ranges are required, a write to the range
registers is necessary. This is shown in the first two serial transfers
of Figure 44.
These two initial serial transfers are only necessary if input ranges
other than the default ranges are required. After the analog input
ranges are configured, a write to the sequence register is necessary
to select the channels to be included in the sequence. Once the
channels for the sequence have been selected, the sequence can
be initiated by writing to the control register and setting Seq1
to 0 and Seq2 to 1. The AD7328 continues to convert the selected
sequence without interruption provided that the sequence register
remains unchanged and Seq1 = 0 and Seq2 = 1 in the control
register.
AD7328
Rev. 0 | Page 27 of 36
If a write to one of the range registers is required during a se-
quence, it is necessary to first stop the sequence by writing to
the control register and setting Seq1 to 0 and Seq2 to 0. Next,
the write to the range register should be completed to change
the required range. The previously selected sequence should
then be initiated again by writing to the control register and
setting Seq1 to 0 and Seq2 to 1. The ADC converts the first
channel in the sequence.
The AD7328 can be configured to convert a sequence of con-
secutive channels (see Figure 45). This sequence begins by
converting on Channel 0 and ends with a final channel as selected
by Bit ADD2 to Bit ADD0 in the control register. In this config-
uration, there is no need for a write to the sequence register. To
operate the AD7328 in this mode, set Seq1 to 1 and Seq2 to 0
in the control register, and then select the final channel in the
sequence by programming Bit ADD2 to Bit ADD0 in the control
register.
Once the control register is configured to operate the AD7328
in this mode, the DIN line can be held low or the write bit can
be set to 0. To return to traditional multichannel operation, a
write to the control register to set Seq1 to 0 and Seq2 to 0 is
necessary.
When Seq1 and Seq2 are both set to 0, or when both are set
to 1, the AD7328 is configured to operate in traditional multi-
channel mode, where a write to the Channel Address Bit ADD2
to Bit ADD0 in the control register selects the next channel for
conversion.
DIN: WRITE TO RANGE REGISTER 1 TO SELECT THE RANGE
FOR ANALOG INPUT CHANNELS.
DOUT: CONVERSION RESULT FROM CHANNEL 0, 10V
RANGE, SINGLE-ENDED MODE.
CS
DIN: WRITE BIT = 0 OR DIN LINE HELD LOW TO CONTINUE
THROUGH SEQUENCE OF CONSECUTIVE CHANNELS.
DOUT: CONVERSION RESULT FROM CHANNEL 1,
RANGE SELECTED IN RANGE REGISTER 1.
CS
DIN: WRITE TO RANGE REGISTER 2 TO SELECT THE RANGE
FOR ANALOG INPUT CHANNELS.
DOUT: CONVERSION RESULT FROM CHANNEL 0,
RANGE SELECTED IN RANGE REGISTER 1,
SINGLE-ENDED MODE.
CS
DIN: WRITE BIT = 0 OR DIN LINE HELD LOW TO CONTINUE
TO CONVERT THROUGH THE SEQUENCE OF
CONSECUTIVE CHANNELS.
DOUT: CONVERSION RESULT FROM CHANNEL 0,
RANGE SELECTED IN RANGE REGISTER 1.
CS
DIN: WRITE TO CONTROL REGISTER TO SELECT THE FINAL
CHANNEL IN THE CONSECUTIVE SEQUENCE, SET Seq1 = 1
AND Seq2 = 0. SELECT OUTPUT CODING FOR SEQUENCE.
DOUT: CONVERSION RESULT FROM CHANNEL 0,
RANGE SELECTED IN RANGE REGISTER 1,
SINGLE-ENDED MODE.
CS
POWER ON
DIN TIED LOW/WRITE BIT = 0.
04
852-
032
CONTINUOUSLY CONVERT
ON CONSECUTIVE SEQUENCE
OF CHANNELS.
DIN: WRITE TO CONTROL
REGISTER TO STOP THE
SEQUENCE, Seq1 = 0, Seq2 = 0.
DOUT: CONVERSION RESULT
FROM CHANNEL IN SEQUENCE.
CS
STOPPING
A SEQUENCE.
Figure 45. Flowchart for Consecutive Sequence of Channels
AD7328
Rev. 0 | Page 28 of 36
REFERENCE
The AD7328 can operate with either the internal 2.5 V on-chip
reference or an externally applied reference. The internal reference
is selected by setting the Ref bit in the control register to 1. On
power-up, the Ref bit is 0, which selects the external reference
for the AD7328 conversion. Suitable reference sources for the
AD7328 include
AD780
,
AD1582
,
ADR431
,
REF193
, and
ADR391
.
The internal reference circuitry consists of a 2.5 V band gap
reference and a reference buffer. When operating the AD7328
in internal reference mode, the 2.5 V internal reference is available
at the REFIN/OUT pin, which should be decoupled to AGND
using a 680 nF capacitor. It is recommended that the internal
reference be buffered before applying it elsewhere in the system.
The internal reference is capable of sourcing up to 90 A.
On power-up, if the internal reference operation is required for
the ADC conversion, a write to the control register is necessary
to set the Ref bit to 1. During the control register write, the con-
version result from the first initial conversion is invalid. The
reference buffer requires 500 s to power up and charge the
680 nF decoupling capacitor during the power-up time.
The AD7328 is specified for a 2.5 V to 3 V reference range. When
a 3 V reference is selected, the ranges are 12 V, 6 V, 3 V, and
0 V to +12 V. For these ranges, the V
DD
and V
SS
supply must be
equal to or greater than the maximum analog input range selected.
V
DRIVE
The AD7328 has a V
DRIVE
feature to control the voltage at which
the serial interface operates. V
DRIVE
allows the ADC to easily
interface to both 3 V and 5 V processors. For example, if the
AD7328 is operated with a V
CC
of 5 V, the V
DRIVE
pin can be
powered from a 3 V supply. This allows the AD7328 to accept
large bipolar input signals with low voltage digital processing.
TEMPERATURE INDICATOR
The AD7328 has an on-chip temperature indicator. The
temperature indicator can be used to give local temperature
measurements on the AD7328. To access the temperature
indicator, the ADC should be configured in pseudo differential
mode, Mode 1 = Mode 0 = 1, which sets Channel Bits ADD2,
ADD1, and ADD0 to 1. V
IN
7 must be tied to AGND or to a
small dc voltage within the specified pseudo input range for the
selected analog input range. When a conversion is initiated in
this configuration, the output code represents the temperature
(see Figure 46 and Figure 47). When using the temperature
indicator on the AD7328, the part should be operated at low
throughput rates, such as approximately 50 kSPS for the 10 V
range and 30 kSPS for the 2.5 V range. The throughput rate is
reduced for the temperature indicator mode because the AD7328
requires more acquisition time for this mode.
4420
4340
40
100
TEMPERATURE (C)
ADC
O
UT
P
UT
CO
DE
4410
4400
4390
4380
4370
4360
4350
20
0
20
40
60
80
10V RANGE, INT REF
V
CC
= V
DRIVE
= 5V
V
DD
/V
SS
= 12V
50kSPS
0
485
2-
0
33
Figure 46. Temperature vs. ADC Output Code for 10 V Range
5450
5100
40
80
TEMPERATURE (C)
ADC
O
UT
P
UT
CO
DE
5400
5350
5300
5250
5200
5150
20
0
20
40
60
V
CC
= V
DRIVE
= 5V
V
DD
/V
SS
= 12V
2.5V RANGE
INT REFERENCE
30kSPS
0
485
2-
0
34
Figure 47. Temperature vs. ADC Output Code for 2.5 V Range
AD7328
Rev. 0 | Page 29 of 36
MODES OF OPERATION
The AD7328 has several modes of operation that are designed
to provide flexible power management options. These options
can be chosen to optimize the power dissipation/throughput
rate ratio for different application requirements. The mode of
operation of the AD7328 is controlled by the power management
bits, Bit PM1 and Bit PM0, in the control register as shown in
Table 11. The default mode is normal mode, where all internal
circuitry is fully powered up.
NORMAL MODE
(PM1 = PM0 = 0)
This mode is intended for the fastest throughput rate perfor-
mance with the AD7328 being fully powered up at all times.
Figure 48 shows the general operation of the AD7328 in
normal mode.
The conversion is initiated on the falling edge of CS, and the track-
and-hold enters hold mode, as described in the Serial Interface
section. Data on the DIN line during the 16 SCLK transfer is
loaded into one of the on-chip registers, provided that the write
bit is set. The register is selected by programming the register
select bits (see Table 8).
1
16
3 CHANNEL I.D. BITS, SIGN BIT + CONVERSION RESULT
DATA INTO CONTROL/SEQUENCE/RANGE1/RANGE2
REGISTER
SCLK
CS
DOUT
DIN
04852-
035
Figure 48. Normal Mode
The AD7328 remains fully powered up at the end of the con-
version, provided that both PM1 and PM0 contain 0 in the
control register.
Sixteen serial clock cycles are required to complete the conversion
and access the conversion result. At the end of the conversion,
CS can idle either high or low until the next conversion.
Once the data transfer is complete, another conversion can be
initiated after the quiet time, t
QUIET
, has elapsed.
FULL SHUTDOWN MODE
(PM1 = PM0 = 1)
In this mode, all internal circuitry on the AD7328 is powered
down. The part retains information in the registers during full
shutdown. The AD7328 remains in full shutdown mode until
the power management bits, Bit PM1 and Bit PM0, in the control
register are changed.
A write to the control register with PM1 = 1 and PM0 = 1 places
the part into full shutdown mode. The AD7328 enters full shut-
down mode on the 15
th
SCLK rising edge once the control register
is updated.
If a write to the control register occurs while the part is in full
shutdown mode with the power management bits, Bit PM1 and
Bit PM0, set to 0 (normal mode), the part begins to power up
on the 15
th
SCLK rising edge once the control register is updated.
Figure 49 shows how the AD7328 is configured to exit full shut-
down mode. To ensure the AD7328 is fully powered up, t
POWER-UP
should elapse before the next CS falling edge.
04
852
-
04
1
CS
1
16
1
SCLK
SDATA
DIN
16
INVALID DATA
CHANNEL IDENTIFIER BITS + CONVERSION RESULT
DATA INTO CONTROL REGISTER
DATA INTO CONTROL/SHADOW REGISTER
t
POWER-UP
THE PART IS FULLY POWERED UP
ONCE
t
POWER-UP
HAS ELAPSED
CONTROL REGISTER IS LOADED ON THE FIRST 15 CLOCKS.
PM1 = 0, PM0 = 0
TO KEEP THE PART IN NORMAL MODE, LOAD PM1 = PM0 = 0
IN CONTROL REGISTER
PART IS IN FULL
SHUTDOWN
PART BEGINS TO POWER UP ON CS
RISING EDGE AS PM0 = PM0 = 0
Figure 49. Full Shutdown Mode
AD7328
Rev. 0 | Page 30 of 36
AUTOSHUTDOWN MODE
(PM1 = 1, PM0 = 0)
Once the autoshutdown mode is selected, the AD7328 auto-
matically enters shutdown on the 15
th
SCLK rising edge. In
autoshutdown mode, all internal circuitry is powered down.
The AD7328 retains information in the registers during
autoshutdown. The track-and-hold is in hold mode during
autoshutdown. On the rising CS edge, the track-and-hold,
which was in hold during shutdown, returns to track as the
AD7328 begins to power up. The power-up from auto
shutdown is 500 s.
When the control registers is programmed to move into
autoshutdown mode, it does so on the 15
th
SCLK rising edge.
Figure 50 shows the part entering the autoshutdown mode. The
AD7328 automatically begins to power up on the CS rising edge.
The t
POWER-UP
is required before a valid conversion, initiated by
bringing the CS signal low, can take place. Once this valid con-
version is complete, the AD7328 powers down again on the 15
th
SCLK rising edge. The CS signal must remain low again to keep
the part in autoshutdown mode.
AUTOSTANDBY MODE
(PM1 = 0, PM0 =1)
In autostandby mode, portions of the AD7328 are powered
down, but the on-chip reference remains powered up. The
reference bit in the control register should be 1 to ensure that
the on-chip reference is enabled. This mode is similar to auto-
shutdown but allows the AD7328 to power up much faster.
This allows faster throughput rates to be achieved.
As is the case with the autoshutdown mode, the AD7328 enters
standby on the 15
th
SCLK rising edge once the control register is
updated (see Figure 50). The part retains information in the
registers during standby. The AD7328 remains in standby until
it receives a CS rising edge. The ADC begins to power-up on
the CS rising edge. On the CS rising edge, the track-and-hold,
which was in hold mode while the part was in standby, returns
to track.
Wake-up time from standby is 700 ns. The user should ensure
that 700 ns have elapsed before bringing CS low to attempt a
valid conversion. Once this valid conversion is complete, the
AD7328 again returns to standby on the 15
th
SCLK rising edge.
The CS signal must remain low to keep the part in standby mode.
Figure 50 shows the part entering autoshutdown mode. The
sequence of events is the same when entering autostandby mode.
In Figure 50, the power management bits are configured for auto-
shutdown. For autostandby mode, the power management bits,
PM1 and PM0, should be set to 0 and 1, respectively.
04
85
2-
0
42
CS
1
16
15
1
16
15
SCLK
SDATA
DIN
VALID DATA
VALID DATA
DATA INTO CONTROL REGISTER
DATA INTO CONTROL REGISTER
t
POWER-UP
CONTROL REGISTER IS LOADED ON THE FIRST 15 CLOCKS.
PM1 = 1, PM0 = 0
PART ENTERS SHUTDOWN MODE
ON THE 15TH RISING SCLK EDGE
AS PM1 = 1, PM0 = 0
PART BEGINS TO POWER
UP ON CS RISING EDGE
THE PART IS FULLY POWERED UP
ONCE
t
POWER-UP
HAS ELAPSED
Figure 50. Entering Autoshutdown/Autostandy Mode
AD7328
Rev. 0 | Page 31 of 36
100
POWER VS. THROUGHPUT RATE
The power consumption of the AD7328 varies with throughput
rate. The static power consumed by the AD7328 is very low, and
a significant power savings can be achieved as the throughput
rate is reduced. Figure 51 and Figure 52 shows the power vs.
throughput rate for the AD7328 at a V
CC
of 3 V and 5 V, respect-
tively. Both plots clearly show that the average power consumed
by the AD7328 is greatly reduced as the sample frequency is
reduced. This is true whether a fixed SCLK value is used or if it
is scaled with the sampling frequency. Figure 51 and Figure 52
show the power consumption when operating in normal mode
for a fixed 20 MHz SCLK and a variable SCLK that scales with
the sampling frequency.
12
0
0
1
048
52
-
05
2
THROUGHPUT RATE (kSPS)
A
V
ER
A
G
E PO
W
E
R
(mW
)
10
8
6
4
2
100 200 300 400 500 600 700 800 900 1000
VARIABLE SCLK
20MHz SCLK
V
CC
= 3V
V
DD
/V
SS
= 12V
T
A
= 25C
INTERNAL REFERENCE
Figure 51. Power vs. Throughput Rate with 3 V V
CC
20
0
0
1000
048
52
-
05
3
THROUGHPUT RATE (kHz)
A
V
ER
A
G
E PO
W
E
R
(mW
)
18
16
14
12
10
8
6
4
2
100
200
300
400
500
600
700
800
900
20MHz SCLK
VARIABLE SCLK
V
CC
= 5V
V
DD
/V
SS
= 12V
T
A
= 25C
INTERNAL REFERENCE
Figure 52. Power vs. Throughput Rate with 5 V V
CC
AD7328
Rev. 0 | Page 32 of 36
SERIAL INTERFACE
Figure 53 shows the timing diagram for the serial interface of
the AD7328. The serial clock applied to the SCLK pin provides
the conversion clock and controls the transfer of information to
and from the AD7328 during a conversion.
The CS signal initiates the data transfer and the conversion
process. The falling edge of CS puts the track-and-hold into
hold mode and takes the bus out of three-state. Then the analog
input signal is sampled. Once the conversion is initiated, it requires
16 SCLK cycles to complete.
The track-and-hold goes back into track mode on the 14
th
SCLK
rising edge. On the 16
th
SCLK falling edge, the DOUT line returns
to three-state. If the rising edge of CS occurs before 16 SCLK cycles
have elapsed, the conversion is terminated and the DOUT line
returns to three-state. Depending on where the CS signal is brought
high, the addressed register may be updated.
Data is clocked into the AD7328 on the SCLK falling edge. The
3 MSBs on the DIN line are decoded to select which register is
addressed. The control register is a 12-bit register. If the control
register is addressed by the 3 MSBs, the data on the DIN line is
loaded into the control on the 15
th
SCLK rising edge. If the se-
quence register or either of the range registers is addressed, the
data on the DIN line is loaded into the addressed register on the
11
th
SCLK falling edge.
Conversion data is clocked out of the AD7328 on each SCLK
falling edge. Data on the DOUT line consists of three channel
identifier bits, a sign bit, and a 12-bit conversion result. The
channel identifier bits are used to indicate which channel
corresponds to the conversion result.
If the Weak/Three-State bit is set in the control register, rather
than returning to true three-state upon the 16
th
SCLK falling
edge, the DOUT line is pulled weakly to the logic level corres-
ponding to ADD3 of the next serial transfer. This is done to
ensure that the MSB of the next serial transfer is set up in time
for the first SCLK falling edge after the CS falling edge. If the
Weak/Three-State bit is set to 0 and the DOUT line returns to
true three-state between conversions, then depending on the
particular processor interfacing to the AD7328, the ADD3 bit
may be valid in time for the processor to clock it in successfully.
If the Weak/Three-State bit is set to 1, then although the DOUT
line has been driven to ADD3 since the previous conversion, it
is nevertheless so weakly driven that another device could take
control of the bus. This will not lead to a bus contention issue
because, for example, a 10 k pull-up or pull-down resister is
sufficient to overdrive the logic level of ADD3. When the Weak/
Three-State bit is set to 1, the ADD3 is typically valid 9 ns after
the CS falling edge, compared with 14 ns when the DOUT line
returns to three-state at the end of the conversion.
ADD1
1
2
3
4
5
13
14
15
16
WRITE
REG
SEL1
REG
SEL2
LSB
DON'T
CARE
MSB
ADD0
SIGN
DB11
DB10
DB2
DB1
DB0
t
2
t
6
t
4
t
9
t
10
t
3
t
7
t
5
t
8
t
1
t
QUIET
t
CONVERT
SCLK
CS
DOUT
THREE-
STATE
THREE-STATE
DIN
ADD2
3 IDENTIFICATION BITS
04
85
2-
03
6
Figure 53. Serial Interface Timing Diagram (Control Register Write)
AD7328
Rev. 0 | Page 33 of 36
MICROPROCESSOR INTERFACING
The serial interface on the AD7328 allows the part to be directly
connected to a range of different microprocessors. This section
explains how to interface the AD7328 with some common
microcontroller and DSP serial interface protocols.
AD7328 TO ADSP-21xx
The ADSP-21xx family of DSPs interface directly to the AD7328
without requiring glue logic. The V
DRIVE
pin of the AD7328 takes
the same supply voltage as that of the ADSP-21xx. This allows
the ADC to operate at a higher supply voltage than its serial inter-
face. The SPORT0 on the ADSP-21xx should be configured as
shown in Table 14.
Table 14. SPORT0 Control Register Setup
Setting Description
TFSW = RFSW = 1
Alternative framing
INVRFS = INVTFS = 1
Active low frame signal
DTYPE = 00
Right justify data
SLEN = 1111
16-bit data-word
ISCLK = 1
Internal serial clock
TFSR = RFSR = 1
Frame every word
IRFS = 0
ITFS = 1
The connection diagram is shown in Figure 54. The ADSP-21xx
has TFS0 and RFS0 tied together. TFS0 is set as an output, and
RFS0 is set as an input. The DSP operates in alternative framing
mode, and the SPORT0 control register is set up as described in
Table 14. The frame synchronization signal generated on the
TFS is tied to CS, and, as with all signal processing applications,
requires equidistant sampling. However, as in this example, the
timer interrupt is used to control the sampling rate of the ADC,
and, under certain conditions, equidistant sampling cannot be
achieved.
AD7328
1
ADSP-21xx
1
SCLK
SCLK0
CS
TFS0
RFS0
DOUT
DIN
DT0
DR0
V
DD
V
DRIVE
1
ADDITIONAL PINS OMITTED FOR CLARITY.
04
85
2-
0
37
Figure 54. Interfacing the AD7328 to the ADSP-21xx
The timer registers are loaded with a value that provides an
interrupt at the required sampling interval. When an interrupt
is received, a value is transmitted with TFS/DT (ADC control
word). The TFS is used to control the RFS and hence the reading
of data.
The frequency of the serial clock is set in the SCLKDIV register.
When the instruction to transmit with TFS is given (AX0 = TX0),
the state of the serial clock is checked. The DSP waits until the
SCLK has gone high, low, and high again before starting the trans-
mission. If the timer and SCLK are chosen so that the instruction
to transmit occurs on or near the rising edge of SCLK, data can
be transmitted immediately or at the next clock edge.
For example, the
ADSP-2111
has a master clock frequency of
16 MHz. If the SCLKDIV register is loaded with the value 3,
an SCLK of 2 MHz is obtained, and eight master clock periods
elapse for every one SCLK period. If the timer registers are loaded
with the value 803, 100.5 SCLKs occur between interrupts and,
subsequently, between transmit instructions. This situation leads
to nonequidistant sampling as the transmit instruction is occurring
on an SCLK edge. If the number of SCLKs between interrupts is
an integer figure of N, equidistant sampling is implemented by
the DSP.
AD7328 TO ADSP-BF53x
The ADSP-BF53x family of DSPs interface directly to the
AD7328 without requiring glue logic, as shown in Figure 55.
The SPORT0 Receive Configuration 1 register should be set up
as outlined in Table 15.
AD7328
1
ADSP-BF53x
1
V
DD
V
DRIVE
SCLK
RSCLK0
DIN
DT0
DOUT
DR0
CS
RFS0
1
ADDITIONAL PINS OMITTED FOR CLARITY.
04
85
2-
03
8
Figure 55. Interfacing the AD7328 to the ADSP-BF53x
Table 15. SPORT0 Receive Configuration 1 Register
Setting
Description
RCKFE = 1
Sample data with falling edge of RSCLK
LRFS = 1
Active low frame signal
RFSR = 1
Frame every word
IRFS = 1
Internal RFS used
RLSBIT = 0
Receive MSB first
RDTYPE = 00
Zero fill
IRCLK = 1
Internal receive clock
RSPEN = 1
Receive enable
SLEN = 1111
16-bit data-word
TFSR = RFSR = 1
AD7328
Rev. 0 | Page 34 of 36
APPLICATION HINTS
LAYOUT AND GROUNDING
The printed circuit board that houses the AD7328 should be
designed so that the analog and digital sections are confined to
certain areas of the board. This design facilitates the use of ground
planes that can be easily separated.
To provide optimum shielding for ground planes, a minimum
etch technique is generally best. All AGND pins on the AD7328
should be connected to the AGND plane. Digital and analog
ground pins should be joined in only one place. If the AD7328
is in a system where multiple devices require an AGND and
DGND connection, the connection should still be made at only
one point. A star point should be established as close as possible
to the ground pins on the AD7328.
Good connections should be made to the power and ground
planes. This can be done with a single via or multiple vias for
each supply and ground pin.
Avoid running digital lines under the AD7328 device because
this couples noise onto the die. However, the analog ground
plane should be allowed to run under the AD7328 to avoid
noise coupling. The power supply lines to the AD7328 device
should use as large a trace as possible to provide low impedance
paths and reduce the effects of glitches on the power supply line.
To avoid radiating noise to other sections of the board, com-
ponents, such as clocks, with fast switching signals should be
shielded with digital ground and never run near the analog inputs.
Avoid crossover of digital and analog signals. To reduce the effects
of feedthrough within the board, traces should be run at right
angles to each other. A microstrip technique is the best method,
but its use may not be possible with a double-sided board. In
this technique, the component side of the board is dedicated to
ground planes, and signals are placed on the other side.
Good decoupling is also important. All analog supplies should
be decoupled with 10 F tantalum capacitors in parallel with
0.1 F capacitors to AGND. To achieve the best results from
these decoupling components, they must be placed as close as
possible to the device, ideally right up against the device. The
0.1 F capacitors should have a low effective series resistance
(ESR) and low effective series inductance (ESI), such as is typical
of common ceramic and surface mount types of capacitors. These
low ESR, low ESI capacitors provide a low impedance path to
ground at high frequencies to handle transient currents due to
internal logic switching.
AD7328
Rev. 0 | Page 35 of 36
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-153-AC
20
1
11
10
6.40 BSC
4.50
4.40
4.30
PIN 1
6.60
6.50
6.40
SEATING
PLANE
0.15
0.05
0.30
0.19
0.65
BSC
1.20 MAX
0.20
0.09
0.75
0.60
0.45
8
0
COPLANARITY
0.10
Figure 56. 20-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-20)
Dimensions show in millimeters
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
AD7328BRUZ
1
40C to +85C
20-Lead TSSOP
RU-20
AD7328BRUZ-REEL
1
40C to +85C
20-Lead TSSOP
RU-20
AD7328BRUZ-REEL7
1
40C to +85C
20-Lead TSSOP
RU-20
EVAL-AD7328CB
2
Evaluation
Board
EVAL-CONTROL BRD2
3
Controller
Board
1
Z = Pb-free part.
2
This can be used as a stand-alone evaluation board or in conjunction with the EVAL-CONTROL board for evaluation/demonstration purposes.
3
This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. To order a complete
evaluation kit, the particular ADC evaluation board (for example, EVAL-AD7328CB), the EVAL-CONTROL BRD2, and a 12 V transformer must be ordered. See the relevant
evaluation board technical note for more information.
AD7328
Rev. 0 | Page 36 of 36
NOTES
2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04852010/05(0)
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