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Information furnished by Analog Devices is believed to be accurate and
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otherwise under any patent or patent rights of Analog Devices.

AD6411

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700

World Wide Web Site: http://www.analog.com

Fax: 781/326-8703

© Analog Devices, Inc., 1998

DECT RF Transceiver

FUNCTIONAL BLOCK DIAGRAM

LNA

RSSI

RX
DATA

TX
DATA

AD6411

PLL

DEMODULATOR

PLL

VCO

CONTROL

INTERFACE

PFD

FEATURES
Fully Compliant with DECT Specifications
Single IC DECT Radio
Integrated UHF VCO (External Resonator)
Integrated Synthesizer Supporting Extended Frequency

Allocation

Built-In Supply Regulation
Direct VCO Modulation for DECT Transmit Path
PLL-Based Demodulator
Use with Low Cost Plastic Packaged SAW Filters
Ultralow Power Design
Operates from +3.0 V to +5.5 V Battery
User-Selectable Power-Down Modes
Small 48-Lead LQFP Package

APPLICATIONS
DECT Cordless Telephones
DECT-Based Wireless Local Loop Systems
DECT-Based Wireless Data Systems

DESCRIPTION

The AD6411 provides the complete transmit and receive RF
signal processing necessary to implement a digital wireless
transceiver based on the Digital Enhanced Cordless Telecom-
munications (DECT) standard.

The AD6411's receive signal path consists of a mixer, IF ampli-
fiers and PLL demodulator. The low noise, high intercept mixer
is a development of the doubly-balanced Gilbert-Cell type. It
has a nominal 16 dBm input-referred 1 dB compression point
and a 8 dBm input referred third-order intercept. The limiter
amplifier provides sufficient gain to drive the PLL demodulator,
which provides selectable analog or sliced outputs. The RSSI
output provides a voltage proportional to the receive signal
strength. It measures nearly 100 dB IF signal strength range
with 14 mV/dB gain scaling.

The transmit path accepts baseband data, which is filtered and
applied to the VCO directly. The VCO operates at half the RF
carrier frequency, and is doubled to avoid pulling due to leakage
from the output.

An on-chip PLL frequency synthesizer provides channel selec-
tion. Operating modes are selected either through a serial bus or
asynchronous control pins. This allows compatibility with most
of the available DECT baseband controller ASICs.

The AD6411 is packaged in a 48-lead LQFP.

REV. 0

AD6411SPECIFICATIONS

= 25 C, 3.0 V < V

BAT

< 5.5 V unless otherwise noted)

Parameter

Conditions

Min

Typ

Max

Units

RECEIVE RF MIXER

RF Input Frequency

1880 to
1930

MHz

Power Gain

SOURCE

= 50

, Z

LOAD

= 200

Input 1 dB Compression Point

SOURCE

= 50

, Z

LOAD

= 200

dBm

Input Third-Order Intercept

SOURCE

= 50

, Z

LOAD

= 200

dBm

SSB Noise Figure

SOURCE

= 50

, Z

LOAD

= 200

Output VSWR

100 MHz120 MHz

1.5:1

Output Impedance

200

Input Impedance

RX IF AMPLIFIERS

Differential Input Impedance

200

Input VSWR

Input Power < 11 dBm

1.5:1

IF Noise Figure

SOURCE

= 200

Differential

RSSI

RSSI Upper Limit

SOURCE

= 200

Differential

dBm

RSSI Lower Limit

SOURCE

= 200

Differential

dBm

RSSI High Level Voltage

Input Power = 0 dBm (at IF Input)

1.7

RSSI Low Level Voltage

Input Power = 90 dBm (at IF Input)

0.3

RSSI Slope

90 dBm < Input Power < 0 dBm (at IF Input)

mV/dB

RSSI Output Impedance

RSSI

= 0.3 V

700

RSSI Output Response Time

Settling to 95% Value for a 40 dB Input Step,
20 pF External Load

PLL DEMODULATOR

PLL Demodulator Phase Detector Gain

@ 90 Degree Relative Phase

115

150

A/rad

Leakage Current at COFF

Charge Pump Disabled

100

Recommended External VCO Gain

1.152

MHz/V

Demodulator Gain

VCO Gain Set to 1.152 MHz/V

1.736

V/MHz

Demodulator Linearity

THD for FM Tone @ 576 kHz,
Peak Deviation 288 kHz

dBc

VOLTAGE REFERENCE

Output Voltage

1.3

1.37

1.44

Output Current

100

TRANSMIT SECTION

Output Power

= 50

dBm

Harmonically Related Spurii

At 0.5

DECT_Tx: (940 MHz950 MHz)

dBc

At 1.5

DECT_Tx: (2820 MHz2850 MHz)

dBc

Other Spurii

100 MHz3000 MHz, Outside DECT Band
1 MHz Measurement Bandwidth

dBc

Output Phase Noise

With UHF Resonator Qu > 30

1.2 MHz

120

dBc/Hz

3.0 MHz

130

dBc/Hz

>4.7 MHz

135

dBc/Hz

VCO Operating Frequency Range

With Suitable External Resonator

700

1200

MHz

Oscillator Push

Using On-Chip Regulator, 250 mV V

BAT

Step Change with 5

s Rise/Fall Time

kHz

Oscillator Pull

VSWR = 2:1 Any Phase

kHz

SYNTHESIZER

Reference Input Impedance

Reference Input Level

100

1000

mV p-p

Reference Input Frequency

MHz

VCO Signal Input Range

700

1200

MHz

Charge Pump Current "Up"

Voltage On Loop Filter (Pin 38) = 1.4 V

1.30

1.0

0.77

Charge Pump Current "Down"

Voltage On Loop Filter (Pin 38) = 1.4 V

0.66

1.0

1.15

Charge Pump Leakage

Output Disabled

BSW Output "High" Voltage

at I

LOAD

< = 2 mA

2.5

REV. 0

AD6411

Parameter

Conditions

Min

Typ

Max

Units

VOLTAGE REGULATORS (VS1, VS2)

Regulated Voltage Output

LOAD

= 60 mA max

2.675

2.725

2.825

Dropout Voltage

LOAD

= 60 mA; BCW68F or

Equivalent Pass Transistor

150

Load Regulation

VS1: 10 mA < I

LOAD

< 60 mA

VS2: 1 mA < I

LOAD

< 15 mA

Line Transient Response

LOAD

= 10 mA ,

BAT

= 250 mV,

Rise/Fall Time = 2

1.5

Line Rejection

LOAD

= 60 mA,

BAT

= 250 mV,

Static Change

0.5

Power Supply Rejection

DC-1 MHz

POWER CONSUMPTION

Supply Voltage

BAT

3.0

5.5

All Off Mode

Standby Mode

100

200

400

Prior to TX Slot

Active TX Slot

Prior to RX Slot

Active RX Slot

(Synthesizer Dividers On, Charge Pump Off)

OPERATING TEMPERATURE RANGE

+85

ABSOLUTE MAXIMUM RATINGS

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.5 V
Internal Power Dissipation

. . . . . . . . . . . . . . . . . . . . 600 mW

Operating Temperature Range . . . . . . . . . . . 25

C to +85

Storage Temperature Range . . . . . . . . . . . . 65

C to +150

Lead Temperature, Soldering 60 sec . . . . . . . . . . . . . . +300

NOTES

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended rating conditions for extended periods may affect device
reliability.

Thermal Characteristics: 48-lead LQFP package:

= +126

C/W.

ORDERING GUIDE

Temperature

Package

Model

Range

Description

Option

AD6411AST 25

C to +85

48-Lead Plastic LQFP

ST-48

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD6411 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

PIN CONFIGURATION

48-Lead LQFP (ST-48)

13 14 15 16 17 18 19 20 21 22 23 24

48 47 46 45 44

39 38 37

43 42 41 40

PIN 1
IDENTIFIER

TOP VIEW

(Not to Scale)

BSW

DATA

VF2

VCCPD

VCOB

VCCVCO

VCO

GND

VBAT1

GND

VCCTX

GND

TXOP

GND

RX ENAB

GND

RSSI

VCCIF2

GND

IFINB

IFIN

VCCIF1

REF

SFS

DEMOD DATA

TX ENAB

COFF

DMR

IFLF

IFCP

IFVCO

VREF

GND

RFIN

GND

VCCRX

VS1

VF1

SYN

ENAB

VBAT2

CLK

AD6411

MXOP

VCCDM

GND

WARNING!

ESD SENSITIVE DEVICE

AD6411

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PIN FUNCTION DESCRIPTIONS

Pin No.

Label

Description

Type

Comments

REF

DECT Reference Clock Input

Input

SFS

S-Field Sample

Input

HIGH = Sample; LOW = Hold

DEMOD_DATA

Demodulator Output OR Sliced Demodulator

Output

Mode Controlled by DSD Bit in

Output

Control Register

TX_ENAB

Transmit Section Power Control Input

Input

Active-High or Active-Low Set by
TSB Bit in Setup Word

COFF

Demodulator Offset Capacitor

Output

Connect to External Capacitor

DMR

Input for IF PLL Loop Filter Voltage after Data Filter

Input

IFLF

Drive for IF PLL Active Loop Filter

Output

IFCP

Virtual Ground for IF PLL Active Loop Filter

Input

IFVCO

External Resonator for Demodulator VCO

Input

VREF

Voltage Reference Output

Output

1.3 V; Can Be Used for A/D Converter
Reference in Soft-Decision Applications

11, 15, 18,
25, 27, 29,
31, 33, 34,
36, 39

GND

Ground

Power

VCCDM

PLL Demodulator Supply

Power

Normally Connected to VS1

RSSI

Receive Signal Strength Indicator Output

Output

VCCIF2

IF Supply 2

Power

Normally Connected to VS1

IFINB

IF Input

Input

Balanced Input from IF SAW Filter

IFIN

IF Input

Input

Balanced Input from IF SAW Filter

VCCIF1

IF Supply 1

Power

Normally Connected to VS1

VS1

Regulator Sense

Input

Connect to Collector of VS1 Pass Device

VF1

Regulator Force

Output

Connect to Base of VS1 Pass Device

SYN_ENAB

Synthesizer Section Power Control Input

Input

Active-High or Active-Low Set by
SSB Bit in Setup Word

VBAT2

Connect to Battery

Power

MXOP

Receive Mixer Output

Output

VCCRX

Receive RF Supply

Power

Normally Connected to VS1

RFIN

Receive Mixer Input

Input

RX_ENAB

Receive Section Power Control Input

Input

Active-High or Active-Low Set by RSB
Bit in Setup Word

TXOP

Transmit Output

Output

Open Collector Output

VCCTX

Transmit Supply

Power

Normally Connected to VS1

VCCPD

Phase Detector and Charge Pump Supply

Power

Normally Connected to VS1

Loop Filter (from Charge Pump Output)

Output

VCOB

UHF Oscillator

Input

VCO Tank Circuit

VCCVCO

Supply for Second Regulator Sense

Power

Connect to Collector of VS2 Pass Device

VCO

UHF Oscillator

Input

VCO Tank Circuit

BSW

Resonator Band Switch Output

Output

Controls Tank Circuit Band Segment

VF2

Regulator Force

Output

Connect to Base of VS2 Pass Device

VBAT1

Connect to Battery

Power

3-Wire Bus Enable

Input

DATA

3-Wire Bus Data

Input

CLK

3-Wire Bus Clock

Input

AD6411

REV. 0

PRODUCT OVERVIEW

The AD6411 provides most of the active circuitry required to
realize a complete low power DECT transceiver.

Figure 1 shows the main sections of the AD6411. It consists, in
the receive path, of a UHF mixer and two-stage IF strip with
integrated demodulator and data slicer. The transmit path con-
sists of a VCO, frequency doubler and buffer amplifier.

Channel selection is performed by an on-chip PLL synthesizer.
All AD6411 operating modes can be controlled by parallel con-
trol inputs or the serial interface.

Receive Mixer

The UHF mixer is an improved Gilbert-cell design. The dy-
namic range at the input of the mixer is determined, at the up-
per end, by the maximum input signal level of 16 dBm in 50

at RFIN up to which the mixer remains linear and a valid RSSI
signal is provided and, at the lower end, by the noise level.

The local oscillator input of the receive mixer is internally pro-
vided by the LO, which is obtained by doubling the on-chip
VCO frequency.

The output of the mixer is single-ended. The nominal conver-
sion gain is specified for operation into a 110.592 MHz or
112.32 MHz SAW IF DECT bandpass filter. The power gain
of 17 dB is measured between the mixer input and the input of
this filter.

IF Circuits and Demodulator

Demodulation is achieved via a PLL. This is shown in detail in
Figure 2. An external manufacturing trim is required to achieve
the required level of frequency accuracy. The approach is to
adjust the capacitor TC1 (with the presence of an unmodulated
carrier) such that the dc level at Pin 3 (DEMOD_DATA) is
equal to the voltage on the external reference pin VREF.

Two demodulation modes are supported. In one mode any
frequency offset due to reference drift or frequency offsets on
the incoming carrier are propagated to the output (referred to as
"Normal" demodulation). The other method is to use a feature
of the DECT system that enables a secondary compensation
circuit to track out frequency offsets ("S-field sampling," which
is enabled by the pin SFS--active high together with the con-
figuration bit SFM set over the serial interface).

BPF1 LNA BPF2

VCC

BSW

TXDATA

VCC

SAW

C13

C14

VCC

TCI

C10

REF

RSSI

ENAB

DATA

CLK

ENAB

SYN

ENAB

VBAT

DMOD DATA

SFS

R4 VREF

VBAT

REFERENCE

REGULATOR #2

REGULATOR #1

DC RESTORE

CONTROLLER

INTERFACE

LOAD

SYNTH

0...31

32/34

12/16

PFD

C11

AD6411

32/33

C12

Figure 1. Functional Block Diagram

AD6411

REV. 0

The block diagram shows the principle of operation of these two
modes together with the internal switch settings as shown in
Figure 2.

Table I. Supported Demodulation Modes

Mode

SW1

SW2

SW3

Comment

Prior to RX

Open

Closed Closed Precharge Loop

SFS = Don't Care

Filter and C Offset

SFM = 0

Capacitor

Normal Demod

Open

Closed Open

Use Temperature

Active RX

Compensated

SFS = Don't Care

Reference Voltage

SFM = 0

S-Field Sample

Closed Open

Open

SFS = 1
SFM = 1

S-Field Hold

Open

SFS = 0
SFM = 1

An important consideration in normal demodulation mode is
any drift after the initial setup of the VCO. One mechanism is
the Capacitance vs. Temperature coefficient of the external
varactor. This has a known characteristic which is compensated
by an internal reference voltage generation circuit.

UHF VCO

A single UHF VCO oscillator is provided operating at one-half
the required frequency. Therefore, in transmit mode the
oscillator operates from (approximately) 940 MHz to 950 MHz,
and in receive mode the oscillator operates from (approxi-
mately) 884 MHz895 MHz. This requires a switched resona-
tor design, and band switch control is provided by the AD6411.

A balanced oscillator configuration is used which has the advan-
tages of rejection of common-mode interference and noise, and
less coupling to and from other parts of the IC and radio.

Transmit Functions

The DECT transmit function is achieved by direct modulation
of the UHF VCO operating at half the final transmit output
frequency. An on-chip doubler converts this to the final carrier
frequency. In this mode the synthesizer is set to a high imped-
ance mode i.e., "fly-wheeled." The drift is sufficiently low for
both single-slot and double-slot transmit operation.

Synthesizer and LO Functions

A complete synthesizer is implemented on the IC that is capable
of generating all the required DECT channel allocations (in-
cluding the extended DECT bands). This synthesizer can use
reference frequencies of either 13.824 MHz or 10.368 MHz,
controlled by the RD bit in the control register.

Synthesizer Programming

The required channels are programmed by setting the RD bit in
the control register to the correct value, then programming the
A and M Counters as shown below through the serial interface.

VCC

150nH

IFVCO

IF/110.592MHz

TC1

8pF

6.8pF

ZC830

DATA FILTER

LOOP

FILTER

IFCP

96.768MHz

13.824MHz

GM1

IFLF

SW3

SW2

GM2

SW1

GM3

DMR

VREF

DEMOD DATA

COFF

VARACTOR

TEMP Co

COMPENSATION

AD6411

VREF

Figure 2. PLL Demodulator Block Diagram

AD6411

REV. 0

Transmit

DECT
Channel

A Counter

M Counter

Frequency/MHz

1881.792

1883.520

1885.248

1886.976

1888.704

1890.432

1892.160

1893.888

1897.344

The A Counter range is 031, allowing the AD6411 to be used
in the extended DECT bands, up to the following maximum
frequency:

A Counter

M Counter

Frequency/MHz

1933.632

Receive (Local Oscillator Frequency)

Main values are shown for a 110.592 MHz IF frequency. Values
in parentheses are for the 112.32 MHz.

DECT
Channel

A Counter

M Counter

Frequency/MHz

1 (0)

1771.200 (1769.472)

2 (1)

1772.928 (1771.200)

3 (2)

1774.656 (1772.928)

4 (3)

1776.384 (1774.656)

5 (4)

1778.112 (1776.384)

6 (5)

1779.840 (1778.112)

7 (6)

1781.568 (1779.840)

8 (7)

1783.296 (1781.568)

9 (8)

1785.024 (1783.296)

10 (9)

1786.752 (1785.024)

Serial Interface

The IC operating modes can be controlled via the 3-wire
serial interface or via the three external control lines provided
(TX_ENAB, RX_ENAB, SYN_ENAB). The three external
control lines allow mode control of the IC if the baseband con-
troller cannot access the serial interface between slots. In either
case the 3-wire serial interface is used to program the channel
number. Detailed below is the register setup and the serial
interface operation.

The serial interface consists of a 16-bit shift register and two
registers for configuration of the IC and mode control. This
allows mode control of the IC with a single 16-bit write. DATA
is the serial data input (data MSB first), CLK is the shift regis-
ter clock (positive edge trigger), EN (positive edge trigger) is the
serial interface enable. All internal register values are retained
when sections of the IC are powered down. Figure 3 shows the
timing diagram for the serial interface.

HEN

DST

DHD

CLK

DEN

CLK

DATA

MSB

LSB

Figure 3. Serial Interface Timing Diagram

Parameter

Symbol

Typ

Unit

Maximum Serial Clock Frequency

f_clk

13.824

MHz

Serial Data Set Up Time

t_dst

Serial Data Hold Time

t_dhd

Enable Set Up to Clock High

t_hen

Clock Low to Enable Low

t_den

The Least Significant Bit of the serial control word selects either
the "one-time setup" register or the operating mode register,
with the remaining 15 bits as data. Table II below details the
internal IC register mapping.

Table II. Register Mapping

Address (D0)

Function

Comments

One-Time IC Setup

See Table III

IC Operating Mode

See Table IV

AD6411 INITIAL SETUP

On power-up the state of the IC is not defined. A one-time setup
register must be loaded through the serial interface port, and is
selected when the LSB of the serial word is 0. After this one-
time setup, a single serial word controls operation of the IC.

Table III. One-Time IC Setup Register

D15

D14

D13

D12

D11

D10

RSB

TSB

SSB

RXM1 RXM0 TXM

BSWS

CF0

CT1

CT0

DSD

SFM

PDS

AD6411

REV. 0

One-Time Setup Register Bit Definitions

RSB: Receive Control Line Sense Bit

RSB

Function

Receive Section POWER UP Active HIGH

Receive Section POWER UP Active LOW

TSB: Transmit Control Line Sense Bit

TSB

Function

Transmit Section POWER UP Active HIGH

Transmit Section POWER UP Active LOW

SSB: Synthesizer Control Line Sense Bit

SSB

Function

Synthesizer POWER UP Active LOW

Synthesizer POWER UP Active HIGH

RXM1, RXM0: Divider Power Mode In Active Receive Slot

RXM1

RXM0

Function

Dividers Powered Down, VCO Fly-
wheeled in Active Receive Mode

Dividers Powered Up, VCO Fly-
wheeled in Active Receive Mode

Dividers Powered Up, VCO Locked
to Synthesizer in Active Receive Mode

TXM: Divider Power Mode In Active Transmit Slot

TXM

Function

Dividers Powered Down, VCO Flywheeled in
Active Mode

Dividers Powered Up, VCO Flywheeled in Active
Mode

BSWS: Band Switch Sense (Control with External Lines)

BSWS

Function

Band Switch Output High in Receive Slot, PIN
Diode ON

Band Switch Output Low in Receive Slot, PIN
Diode ON

CF0: Configuration Bit 0

CF0

Function

Use Serial Interface for Mode Control

Use External Control Lines for Mode Control

CT1, CT0: Charge Pump Test Bits

CT1

CT0

Function

Three-State Output

Force Pump UP Current (Nom 1 mA)

Force Pump DOWN Current (Nom 1 mA)

Normal Operation (Driven from PFD)

DSD: Disable Data Slicer

DSD

Function

Disable On-Chip Data Slicer. Analog Output at Pin
DEMOD_DATA

Enable On-Chip Data Slicer. Digital Output at Pin
DEMOD_DATA

DSD bit is configured at power-up depending on whether an
external data slicer is being used in the system. Data slicer is
disabled when the IF strip is powered down irrespective of the
status of bit DSD.

SFM: S-Field Mode

SFM

Function

Normal Demodulation Mode

S-Field Sampling Mode

PDS: Phase Detector Sense

PDS

Function

PFD Pumps UP when Fvco > Fref

PFD Pumps UP when Fref > Fvco

RD: Reference Divide Ratio

Function

Reference Frequency = 10.368 MHz

Reference Frequency = 13.824 MHz

AD6411

REV. 0

CONTROLLING THE AD6411 OPERATING MODE

Table IV. Operating Mode Control Register

D15

D14

D13

D12

D11

D10

IF/RSSI RXMixer

DMOD

DIV

UHF

BSW

REGS

BUF

VCO

The operating mode register, loaded through the serial port
when the LSB is "1," allows any circuit block to be indepen-
dently powered on or off. This can be bypassed to enable mode
control of the IC via the three external control lines. Transitions
between major DECT modes can be made with a single word
program (including channel change) when using the serial inter-
face only. Table V defines the bit status for the various IC oper-
ating modes when used with the serial interface only.

Table V. Bit Status for the Different Operating Modes

Data Bits
(D9 . . . D0)
Operating
Mode Register

Function

Comments

00 0000 0101

All Off Mode

All Circuits Off

00 0000 0111

Stand-By Mode

Regulators On

00 0111 1111

Prior to TX Slot

VCO, TX Buffer,
Dividers, Charge Pump,
Regulators Active,
VREF (1.4 V) Active

00 0101 1111

Active TX Slot

VCO, TX Buffer, Di-
viders, Regulator
Circuits Active,
VREF (1.4 V) Active

00 1110 1011

Prior to RX Slot

VCO

, Dividers, Charge

Pump, Regulators, De-
modulator Precharge
Circuits Active,
VREF (1.4 V) Active

11 1100 1011

Active RX Slot

RX Mixer, VCO

, Divid-

ers, Regulators, De-
modulator, Receive
Strip Circuits Active,
VREF (1.4 V) Active

NOTES

Alternatively it may be possible to power-down the dividers in an active trans-

mit slot depending on the effect of thermal transients on VCO pulling. In this
mode the dividers are biased but inactive. This can also be implemented when
external control lines are used with bits TXM, RXM1, RXM0.

Band switch output is determined by the status of BSW. Band switch output is

Low when BSW is high, high when BSW is low. In Table V, band switch
output is high for AcRx and PrRx slots, otherwise it is low.

CHANNEL SELECTION/FREQUENCY CONTROL

The M0 and A4A0 bits in the operating mode register control
the channel selection for the AD6411 synthesizer. The M0 bit
selects the M Counter division ratio.

M0: M Counter Divide Ratio

Function

M Divide Ratio 32

M Divide Ratio 34

The A4 through A0 bits control the A counter division ratio,
and control the channel selection. Refer to the section of this
data sheet on Synthesizer Programming for a mapping of chan-
nel frequency to synthesizer divider words.

A4A0: A Counter Division Ratio

"A"

ANALOG/RF INTERFACE DETAILS

The AD6411 is an advanced 1.9 GHz radio transceiver circuit
and requires careful attention to the selection of external com-
ponents. The AD6411 is readily capable of performance that
meets the ETS-300-176-1 (formerly TBR06) DECT radio
specifications. This section of the data sheet will describe sug-
gestions for external componentry that will allow the design of a
complete DECT RF transceiver.

Low Noise Amplifier

An external LNA is required to meet the RF leakage specifica-
tions in ETS-300-176-1. The following circuit, based on a Si-
emens BFP405 discrete transistor, is representative of a suitable
LNA. The SC1.89 SAW filter removes images prior to the down
converter. The filter is matched to the AD6411 input with a
printed inductor and fixed capacitor. Complete details of the
circuit, with transmission-line dimensions, can be found in
Siemens Application Note No. 020.

RF IN

22pF

TL2

TL3

TL1

39k

100pF

100

TL6

BFP405

33pF

TL5

10pF

10nF

+3V

RF OUT

TL4

33pF

Figure 4. LNA circuit

AD6411

REV. 0

UHF VCO Tank Circuit

The UHF VCO is probably the most critical part of an AD6411-
based DECT radio. The design shown in Figure 5 uses a
printed inductor, a BBY53 (or equivalent) common-cathode
dual varactor, and a PIN-diode (BAR63-03W or equivalent)
band switch to cover the DECT band. The capacitance added
to the tank circuit by the PIN-diode is needed to switch the VCO
to the DECT receive band. It is switched out of the circuit in the
transmit mode, in which the VCO is directly modulated by
baseband transmit data. With this scheme, no manufacturing
trim is needed to tune the VCO to the DECT band. Tank com-
ponent values will need slight modification to cover the "ex-
tended DECT" frequency bands. The dimensions of tank
inductor L1 will depend on the circuit board material and thick-
ness used. Contact Analog Devices for assistance on UHF tank
inductor layout.

2pF

20k

8.2pF

10k

BAR80

BAR63-03W

6.8pF

1nF

6.8k

330pF

10k

1.2pF

2pF

VCCVCO

VCOB

BSW

VCO

AD6411

TX
DATA
IN

Figure 5. UHF VCO Circuit

Power Management

The AD6411 reduces the external components needed for
power management in a DECT radio by integrating voltage
regulators on-chip. The circuit can therefore operate directly
from a 3.0 V to 5.5 V unregulated battery supply.

There are two regulators. The first, VS1 (Pins 20, 21 and 23),
uses an external BCW68F (or similar) PNP pass transistor to
provide a regulated 2.75 V nominal supply voltage to most of
the AD6411 circuitry. The second regulator, VS2 (Pins 41, 44,
and 45), is intended to provide the regulated voltage to the
UHF VCO section and should not be used for other circuitry.

REGULATOR #1

REGULATOR #2

10nF

VBAT

10nF

10pF

1nF

PASS TRANSISTORS: BCW68F OR EQUIVALENT

TO PIN 40 (VCOB)

AD6411

Figure 6. Voltage Regulator Circuitry

Transmit/Receive Switching

Since the same antenna is used for both transmit and receive, a
switch consisting of PIN diodes and printed transmission lines is
used to disconnect the receive path from the antenna during
transmit periods. A suggested circuit is shown in Figure 7.
Complete details can be found in Siemens Application Note
No. 007.

FROM PA

BAR63-03W

ANT

27nH

47pF

470pF

TX/RX
1=TX
0=RX

TO RX IN

BAR80

Figure 7. T/R Switch

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: AD6411

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: AD6411