FUNCTIONAL BLOCK DIAGRAM

LRCK

BCK

64/32

DGND

AGND

APD

VINR

VINR+

REFR

WCK

DATA

CLOCK

DGND

AGND

VINL

VINL+

REFL

VOLTAGE

REFERENCE

SERIAL OUTPUT

INTERFACE

SINGLE-STAGE,

4k-TAP

FIR DECIMATION

FILTER

DIGITAL

CHIP

ANALOG

CHIP

RESET

SINGLE-STAGE,

4k-TAP

FIR DECIMATION

FILTER

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

High Performance

16-/18-Bit

Stereo ADCs

AD1878/AD1879*

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700

Fax: 617/326-8703

FEATURES
Fully Differential Dual Channel Analog Inputs
103 dB Signal-to-Noise (AD1879 typ)
98 dB THD+N (AD1879 typ)
0.001 dB Passband Ripple and 115 dB Stopband

Attenuation

Fifth-Order, 64 Times Oversampling

Modulator

Single Stage, Linear Phase Decimator
256 F

Input Clock

APPLICATIONS
Digital Tape Recorders

Professional, DCC, and DAT

A/V Digital Amplifiers
CD-R
Sound Reinforcement

PRODUCT OVERVIEW

The AD1879 is a two-channel, 18-bit oversampling ADC based
on

technology and intended primarily for digital audio appli-

cations. The AD1878 is identical to the 18-bit AD1879 except
that it outputs 16-bit data words. Statements in this data sheet
should be read as applying to both parts unless otherwise noted.

Each input channel of these ADCs is fully differential. Each
data conversion channel consists of a fifth order one-bit noise
shaping modulator and a digital decimation filter. An on-chip
voltage reference provides a voltage source to both channels sta-
ble over temperature and time. Digital output data from both
channels is time-multiplexed to a single, flexible serial interface.
The AD1878/AD1879 accepts a 256

input master clock.

Input signals are sampled at 64

on switched-capacitors,

eliminating external sample-and-hold amplifiers and minimizing
the requirements for antialias filtering at the input. With simpli-
fied antialiasing, linear phase can be preserved across the passband.
The AD1878/AD1879's proprietary fifth-order differential
switched-capacitor modulator architecture shapes the one-bit
comparator's quantization noise out of the audio passband. The
high order of the modulator randomizes the modulator output,
reducing idle tones in the AD1878/AD1879 to very low levels.
The AD1878/AD1879's differential architecture provides in-
creased dynamic range and excellent common-mode rejection
characteristics. Because its modulator is single-bit, AD1878/
AD1879 is inherently monotonic and has no mechanism for
producing differential linearity errors.

The digital decimation filters are single-stage, 4095-tap finite
impulse response filters for filtering the modulator's high fre-
quency quantization noise and reducing the 64

single-bit

output data rate to a F

word rate. They provide linear

Protected by U.S. Patent Numbers 5055843, 5126653, and others pending.

phase and a narrow transition band that permits the digitization
of 20 kHz signals while preventing aliasing into the passband
even when using a 44.1 kHz sampling frequency. Passband
ripple is less the 0.001 dB, and stopband attenuation exceeds
115 dB.

The flexible serial output port produces data in twos-complement,
MSB-first format. Input and output signals are to TTL and
CMOS-compatible logic levels. The port is configured by pin
selections. The AD1878/AD1879 can operate in either master
or slave mode. Each 16-/18-bit output word of a stereo pair can
be formatted within a 32-bit field as either right-justified, I

S-

compatible, or at user-selected positions. The output can also be
truncated to 16-bits by formatting into a 16-bit field.

The AD1878/AD1879 consists of two integrated circuits in a
single ceramic 28-pin DIP package. The modulators and refer-
ence are fabricated in a BiCMOS process; the decimator and
output port, in a 1.0

m CMOS process. Separating these func-

tions reduces digital crosstalk to the analog circuitry. Analog and
digital supply connections are separated to further isolate the
analog circuitry from the digital supplies.

The AD1878/AD1879 operates from

5 V power supplies over

the temperature range of 25

C to +70

REV. 0

AD1878/AD1879SPECIFICATIONS

TEST CONDITIONS UNLESS OTHERWISE NOTED

Supply Voltages

Ambient Temperature

Input Clock (F

CLOCK

)

12.288

MHz

Input Signal

974

0.5

dB Full Scale

All minimums and maximums tested except as noted.

ANALOG PERFORMANCE

Min

Typ

Max

Units

AD1879 Resolution

Bits

AD1878 Resolution

Bits

Clock Input Frequency Range

CLOCK Input (F

CLOCK

)

0.01

12.288

14.286

MHz

Modulator Sample Rate (F

CLOCK

/4)

0.0025

3.072

3.5715

MHz

Output Word Rate (F

= F

CLOCK

/256)

0.039

55.8

kHz

AD1879 Dynamic Range (0 kHz to 20 kHz, 60 dB input)

Stereo Mode (No A-Weight Filter)

100

103

Mono Mode

(No A-Weight Filter)

106

Stereo Mode (with A-Weight Filter)

105

AD1879 Trimmed

Signal to (Noise + Distortion)

Full Scale

20 dB

AD1879 Untrimmed

Signal to (Noise + Distortion)

Full Scale

20 dB

AD1879 Trimmed

Signal to Total Harmonic Distortion

Full Scale

20 dB

100

AD1878 Dynamic Range (0 kHz to 20 kHz, 60 dB 1.0936 kHz

Input Dithered with a 10 dB 21.873 kHz Sine Wave)
Stereo Mode (No A-Weight Filter)

AD1878 Trimmed

Signal to (Noise + Distortion)

Full Scale

20 dB

AD1878 Untrimmed

Signal to (Noise + Distortion)

Full Scale

20 dB

AD1878 Trimmed

Signal to Total Harmonic Distortion

Full Scale

20 dB

100

Analog Inputs

Differential Input Range

5.985

6.3

6.615

Input Impedance at Each Input Pin

7.0

DC Accuracy

Gain Error

Interchannel Gain Mismatch

0.05

0.15

Gain Drift

150

ppm/

AD1879 Midscale Offset Error

200

750

18-Bit LSBs

AD1878 Midscale Offset Error

200

16-Bit LSBs

Midscale Drift

ppm/

Voltage Reference

2.4

2.86

3.2

Crosstalk (EIAJ Method)

100

105

Interchannel Phase Deviation

0.001

Degrees

NOTES

Both channels connected together for mono operations as described below in "How to Extend SNR."

Differential gain imbalance manually trimmed to eliminate second harmonic. See "Applications Issues" below.

Test performed without part-to-part trimming.

The differential input range is twice the range seen at each input pin. The input range corresponds to the full-scale digital output range.

Specifications subject to change without notice.

AD1878/AD1879

DIGITAL INPUTS

Min

Max

Units

0.8

@ V

= 5 V

@ V

= 0 V

@ I

= 360

4.0

@ I

= 1.6 mA

0.5

DIGITAL TIMING

Min

Typ

Max

Units

CLOCK

Period (T

CLOCK

= 1/F

CLOCK

)

0.07

100

LO Pulse Width

HI Pulse Width

BCK Pulse Width

CLOCK Periods

64-Bit Frame LRCK Pulse Width

BCK Periods

32-Bit Frame LRCK Pulse Width

BCK Periods

WCK Pulse Width

BCK Periods

RSET

RESET

Setup to CLOCK Rising

RHLD

RESET

Hold from CLOCK Rising

RSLS

RESET

Pulse Width

CLOCK Periods

WSET

WCK to CLOCK Rising

WHLD

WCK Hold from CLOCK Rising

DLYCK

CLOCK to BCK/WCK/LRCK Delay

(Master Mode)

SET

BCK/LRCK to CLOCK Falling

(Slave Mode)

HLD

BCK/LRCK Hold from CLOCK Falling

(Slave Mode)

DLYD,

MSB

CLOCK Falling to MSB DATA Delay

DLYD

CLOCK Rising to DATA Delay, Except MSB

POWER

Min

Typ

Max

Units

Supplies

Voltage, DV

/AV

1/AV

4.75

5.25

Voltage, AV

1/AV

5.25

4.75

Current, AV

1/AV

Current, AV

1/AV

1--Power Down

Current, AV

2/AV

Current, DV

Dissipation

Operation

1,130

1,370

Operation--Analog Supplies

810

1,020

Operation--Digital Supplies

320

350

Power Down (All Supplies)

530

680

Power Supply Rejection

1 kHz 300 mV p-p Signal at Analog Supply Pins

102

dBFS

Passband--Any 300 mV p-p Signal

dBFS

Stopband--Any 300 mV p-p Signal

105

dBFS

TEMPERATURE RANGE

Min

Typ

Max

Units

Specifications Guaranteed

+25

Functionality Guaranteed

+70

Storage

+100

REV. 0

AD1878/AD1879

REV. 0

ABSOLUTE MAXIMUM RATINGS

Min

Typ

Max

Units

to DGND and AV

1/AV

2 to AGND

1/AV

2 to AGND

2 to AV

0.3

Digital Inputs to DGND

0.3

+ 0.3

Analog Inputs

1 0.3

1 + 0.3

AGND to DGND

0.3

Reference Voltage

Indefinite Short Circuit to Ground

Soldering

+300

sec

DIGITAL FILTER CHARACTERISTICS

Min

Typ

Max

Units

Decimation Factor

Passband Ripple

0.001

Stopband

Attenuation

115

48 kHz F

(12.288 MHz CLOCK)

Passband

21.7

kHz

Stopband

26.2

3,045

kHz

44.1 kHz F

(11.2896 MHz CLOCK)

Passband

20.0

kHz

Stopband

24.1

2,798

kHz

32 kHz F

(8.192 MHz CLOCK)

Passband

14.5

kHz

Stopband

17.5

2,030

kHz

Other F

Passband

0.4535

Stopband

0.5458

63.4542

Group Delay ([4096/2]/[64

])

32/F

Group Delay Variation

NOTE

Stopband repeats itself at multiples of 64

where F

is the output word rate. Thus the digital filter will attenuate to 115 dB across the frequency spectrum

except for a range

0.5458

wide at multiples of 64

Specifications subject to change without notice.

ORDERING GUIDE

Package

Model

Temperature

Description

Option

AD1878JD

C to +70

Ceramic DIP

D-28

AD1879JD

C to +70

Ceramic DIP

D-28

WARNING!

ESD SENSITIVE DEVICE

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1878/AD1879 features proprietary ESD protection circuitry, permanent dam-
age may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.

AD1878/AD1879

REV. 0

DEFINITIONS

Dynamic Range

The ratio of a full-scale output signal to the integrated output
noise in the passband (0 kHz to 20 kHz), expressed in decibels
(dB). Dynamic range is measured with a 60 dB input signal
and is equal to (S/[THD+N]) + 60 dB.

Signal to (Noise + Distortion)

The ratio of the root-mean-square (rms) value of the fundamen-
tal input signal to the rms sum of all spectral components in the
passband, expressed in decibels (dB).

Signal to Total Harmonic Distortion (THD)

The ratio of the rms sum of all harmonically related spectral
components in the passband to the fundamental input signal,
expressed either as a percentage (%) or in decibels (dB).

Passband

The region of the frequency spectrum unaffected by the attenu-
ation of the digital decimator's filter.

Passband Ripple

The peak-to-peak variation in amplitude response from equal
amplitude input signal frequencies within the passband, ex-
pressed in decibels.

Stopband

The region of the frequency spectrum attenuated by the digi-
tal decimator's filter to the degree specified by "stopband
attenuation."

Gain Error

With a near full-scale input, the ratio of actual output to ex-
pected output, expressed as a percentage.

Interchannel Gain Mismatch

With near full-scale inputs, the ratio of outputs of the two stereo
channels, expressed in decibels.

Gain Drift

Change in response to a near full-scale input with a change in
temperature, expressed as parts-per-million (ppm) per

Midscale Offset Error

Output response to a midscale input (i.e., zero volts dc), ex-
pressed in least-significant bits (LSBs).

Midscale Drift

Change in midscale offset error with a change in temperature,
expressed as parts-per-million (ppm) of full scale per

Crosstalk

Ratio of response on one channel with a grounded input to a
full-scale 1 kHz sine-wave input on the other channel, expressed
in decibels.

Interchannel Phase Deviation

Difference in input sampling times between stereo channels, ex-
pressed as a phase difference in degrees between 1 kHz inputs.

Power Supply Rejection

With analog inputs grounded, energy at the output when a
300 mV p-p signal is applied to power supply pins, expressed in
decibels of full scale.

Group Delay

Intuitively, the time interval required for an input pulse to ap-
pear at the converter's output, expressed in milliseconds (ms).
More precisely, the derivative of radian phase with respect to
radian frequency at a given frequency.

Group Delay Variation

The difference in group delays at different input frequencies.
Specified as the difference between largest and the smallest
group delays in the passband, expressed in microseconds (

s).

AD1878/AD1879 PIN LIST

Pin Input/Output Pin Name Description

I/O

LRCK

Left/Right Clock

I/O

BCK

Bit Clock

Mode Select 0

64/32

Bit Rate Select

+5 V Digital Supply

DGND

Digital Ground

N/C

No Connection; Do Not Connect

5 V Analog Supply

5 V Analog Logic Supply

AGND

Analog Ground

APD

Analog Power Down

VINR

Right Inverting Input

VINR+

Right Noninverting Input

I/O

REFR

Right Reference Capacitor

I/O

REFL

Left Reference Capacitor

VINL+

Left Noninverting Input

VINL

Left Inverting Input

AGND

Analog Ground

+5 V Analog Supply

+5 V Analog Logic Supply

5 V Analog Supply

+5 V Digital Supply

DGND

Digital Ground

RESET

Reset

Mode Select 1

CLOCK

Master Clock Input

DATA

Serial Data Output

I/O

WCK

Word Clock

THEORY OF OPERATION

Modulator Noise-Shaping

The stereo, differential analog modulators of the AD1878/
AD1879 employ a proprietary feedforward and feedback archi-
tecture that passes input signals in the audio band with a unity
transfer function yet simultaneously shape the quantization
noise generated by the one-bit comparator out of the audio
band. See Figure 1. Without the

architecture, this quantiza-

tion noise would be spread uniformly from dc to one-half the
oversampling frequency, 64

. (Regardless of architecture,

64 times oversampling by itself significantly reduces the quanti-
zation noise in the audio band if the input is properly dithered.
However, the noise reduction is only [log

64]

3 dB = 18 dB.)

PIN 1

0.580 (14.73)

0.485 (12.32)

2
8

0.625 (15.87)
0.600 (15.24)

0.015 (0.381)

0.008 (0.204)

0.195 (4.95)
0.125 (3.18)

0.250

(6.35)

MAX

0.022 (0.558)
0.014 (0.356)

0.100

(2.54)

BSC

0.200 (5.05)
0.125 (3.18)

0.070 (1.77)

MAX

0.060 (1.52)
0.015 (0.38)

0.150
(3.81)
MIN

SEATING
PLANE

1.565 (39.70)
1.380 (35.10)

Figure 1. AD1878/AD1879 Modulator Noise-Shaper (One
Channel)

AD1878/AD1879

REV. 0

The AD1878/AD1879's patented

architectures "shape" the

quantization noise-transfer function in a nonuniform manner.
Through careful design, this transfer function can be specified to
high-pass filter the quantization noise out of the audio band into
higher frequency regions. See Figure 27. The Analog Devices'
AD1878/AD1879 also incorporates feedback resonators from
the third integrator's output to the second integrator's input and
from the fifth integrator's output to the fourth integrators' input.
These resonators do not affect the signal transfer function but
allow flexible placement of zeros in the noise transfer function.
For the AD1878/AD1879, these zeros were placed near the high
frequency end of the audio passband, reducing the quantization
noise in a region where it otherwise would have been increasing.

Oversampling by 64 simplifies the implementation of a high per-
formance audio analog-to-digital conversion system. Antialias
requirements are minimal; a single pole of filtering will usually
suffice to eliminate inputs near F

and its higher multiples.

A fifth-order architecture was chosen both to strongly shape the
noise out of the audio band and to help break up the idle tones
produced in all

architectures. These architectures have a ten-

dency to generate periodic patterns with a constant dc input, a
response that looks like a tone in the frequency domain. These
idle tones have a direct frequency dependence on the input dc
offset and indirect dependence on temperature and time as it
affects dc offset. The human ear operates effectively like a spec-
trum analyzer and can be sensitive to tones below the integrated
noise floor, depending on frequency and level. The AD1878/
AD1879 suppresses idle tones typically 110 dB or better below
full-scale input levels.

Previously it was thought that higher-order modulators could
not be designed to be globally stable. However, the AD1878/
AD1879's modulator was designed, simulated, and exhaustively
tested to remain stable for any input within a wide tolerance of
its rated input range. The AD1878/AD1879 was designed to
reset itself should it ever be overdriven and go unstable. It will
reset itself within 5

s at a 48 kHz sampling frequency. Any such

reset events will be invisible to the user since overdriving the in-
puts will produce a "clipped" waveform at the output.

The AD1878/AD1879 modulator architecture has been imple-
mented using switched-capacitors. A systems benefit is that ex-
ternal sample-and-hold amplifiers are unnecessary since the
capacitors perform the sample-and-hold function Coefficient
weights are created out of varying capacitor sizes. The dominant
noise source in this design is kT/C noise, and the input capaci-
tors are accordingly very large to achieve the AD1878/AD1879's
performance levels. (Each 6 dB improvement in dynamic range
requires a quadrupling of input capacitor size, as well as an
increase in size of the op amps to drive them.) This AD1878/
AD1879 thermal noise has been controlled to properly dither the
input to an 18-bit level. (Note that 16-bit results from either the
AD1878 or AD1879 will be underdithered.)

With capacitors of adequate size and op amps of adequate drive,
a well-designed switched-capacitor modulator will be relatively
insensitive to jitter on the sampling clock. The key issue is
whether the capacitors have had sufficient time to charge or
discharge during the clock period. A properly designed switched
capacitor modulator should be no more sensitive to clock jitter
than are traditional nonoversampled ADCs. This contrasts with

continuous-time modulators, which are very sensitive to the
exact location of sampling clock edges.

See Figures 2023 for illustrations of the AD1878/AD1879's
typical analog performance resulting from this design. Signal-
to-noise+distortion is shown under a range of conditions. Note
the very good linearity performance of the AD1878/AD1879 as
a consequence of its single-bit

architecture in Figure 24.

The common-mode rejection (Figure 25) graph illustrates the
benefits of the AD1878/AD1879's differential architecture. The
excellent channel separation shown in Figure 26 is the result of
careful chip design and layout. The relatively small change in
gain over temperature (Figure 31) results from a robust refer-
ence design.

The output of the AD1878/AD1879 modulators is a stereo
bitstream at 64

(3.072 MHz for F

= 48 kHz). Spectral

analysis of these bits would show that they contain a high qual-
ity replica of the input in the audio band and an enormous
amount of quantization noise at higher frequencies. The input
signal can be recreated directly if these bits are fed into a prop-
erly designed analog low-pass filter.

Digital Filter Characteristics

The digital decimator accepts the modulators' stereo bitstream
and simultaneously performs two operations on it. First, the
decimator low-pass filters the quantization noise that the modu-
lator shaped to high frequencies and filters any other out-of-
audio-band input signals. Second, it reduces the data rate to an
output word rate equal to F

. The high frequency bitstream is

reduced to stereo 16-/18-bit words at 48 kHz (or other desired
F

). The one-bit quantization noise, other high-frequency com-

ponents of the bitstream, and analog signals in the stopband are
attenuated by at least 115 dB.

The AD1878/AD1879 decimator implements a symmetric Finite
Impulse Response (FIR) filter, resulting in its linear phase re-
sponse. This filter achieves a narrow transition band (0.0923

), high stopband attenuation (> 115 dB), and low passband

ripple (< 0.001 dB). The narrow transition band allows the
unattenuated digitization of 20 kHz input signals with F

as low

as 44.1 kHz. The stopband attenuation is sufficient to eliminate
modulator quantization noise from affecting the output. Low
passband ripple prevents the digital filter from coloring the
audio signal. For this level of performance, 4095 22-bit coeffic-
ients (taps) were required in each channel of this filter. The
AD1878/AD1879's decimator employs a proprietary single-
stage, multiplier-free structure developed in conjunction with
Ensoniq Corporation. See Figures 28 and 29 for the digital
filter's characteristics.

The output from the decimator is available as a single serial
output, multiplexed between left and right channels.

Note that the digital filter itself is operating at 64

. As a

consequence, Nyquist images of the passband, transition band,
and stopband will be repeated in the frequency spectrum at
multiples of 64

. Thus the digital filter will attenuate to

115 dB across the frequency spectrum except for a window

0.5458

wide centered at multiples of 64

. Any input

signals, clock noise, or digital noise in these frequency windows
will not be attenuated to the full 115 dB. If the high frequency
signals or noise appear within the passband images within these
windows, they will not be digitally attenuated at all.

AD1878/AD1879

REV. 0

Sample Delay

The sample delay or "group delay" of the AD1878/AD1879 is
dominated by the processing time of the digital decimation fil-
ter. FIR filters convolve a vector representing time samples of
the input with an equal-sized vector of coefficients. After each
convolution, the input vector is updated by adding a new
sample at one end of the "pipeline" and eliminating the oldest
input sample at the other. For an FIR filter, the time at which a
step input appears at the output will be approximately when that
step input is halfway through the input sample vector pipeline.
The input sample vector is updated every 64

. Thus, the

sample delay will be given by the equation,

Group Delay = (4096 2) /(64

) = 32 / F

For the most common sample rates this can be summarized as:

Group Delay

48 kHz

667

44.1 kHz

725

32 kHz

1000

Due to the linear phase properties of FIR filters, the group delay
variation, or differences in group delay at different frequencies is
zero.

OPERATING FEATURES
Voltage Reference

The AD1878/AD1879 includes a +3 V on-board reference
which determines the AD1878/AD1879's input range. This ref-
erence is buffered to both channels of the AD1878/AD1879's
modulator, providing a well-matched reference to minimize
interchannel gain mismatch. The reference should be bypassed
with 10

F tantalum capacitors as shown in Figure 2. The inter-

nal reference can be overpowered by applying an external refer-
ence at the REFR (Pin 14) and REFL (Pin 15) pins, allowing
multiple AD1878/AD1879s to be calibrated to the same gain.
Note that the reference pins still must be bypassed as shown.

Sample Clock

An external master clock supplied to CLOCK (Pin 26) drives
the AD1878/AD1879 modulator, decimator, and digital inter-
face. As with any analog-to-digital conversion system, the sam-
pling clock must be low jitter to prevent conversion errors.

The input clock operates at 256

. The clock is divided down

to obtain the 64

clock required for the modulator. The out-

put word rate will be at F

itself. This relationship is illustrated

for popular sample rates below:

AD1879

Modulator

Output Word

CLOCK Input

Sample Rate

Rate

12.288 MHz

3.072 MHz

48 kHz

11.2896 MHz

2.822 MHz

44.1 kHz

8.192 MHz

2.048 MHz

32 kHz

The AD1878/AD1879 serial interface supports both "master"
and "slave" modes. Note that even in slave mode it is presumed
that the serial interface clocks are derived from the master clock
input, CLOCK. Slave mode does not support asynchronous
data transfers, since asynchronous data transfers would compro-
mise the performance of any high performance converter.

The AD1878/AD1879 decimator makes use of dynamic logic to
minimize die area. There is, therefore, a minimum clock fre-
quency that the AD1878/AD1879 will support specified in
"Specifications" above. Operation of the AD1878/AD1879 at
lower frequencies will cause the device to consume excessive
power and may damage the converter.

Reset

The active LO RESET pin (Pin 24) allows initializing the
AD1879. This is of value only for synchronizing multiple
AD1878/AD1879s in Master Mode--WCK Output. Unless you
are interested in synchronizing multiple AD1878/AD1879s, we
recommend tying RESET HI. The reset function is useful for
nothing else. In fact, there is a maximum specification on
RESET

LO; excessive power consumption may occur with loss

of reliability if left LO too long due to the dynamic logic on the
chip.

Figure 14 illustrates the timing parameters for RESET to
accomplish synchronization of multiple Master Mode--Word
Clock Output ADCs. (This sequence is not necessary for syn-
chronizing multiple AD1878/AD1879s in other modes. See
"Synchronizing Multiple AD1878/AD1879s" below.) Note that
RESET

first has to be LO for at least four CLOCK periods

(three CLOCKs plus t

RSET

plus t

RHLD

, to be more precise).

Then RESET must be HI for a minimum of one CLOCK and a
maximum of two CLOCKs. Then RESET must he LO for at
least another four CLOCKs. From the time when RESET goes
HI again, exactly 127 CLOCKs will occur before LRCK goes
LO.

Analog Power Down

The AD1878/AD1879 features a power-down mode that
reduces current to the analog modulator. It is controlled by
the active HI APD (Pin 11). The power savings are specified in
"Specifications." The converter is still "alive" in the power-
down state but will not produce valid results for all audio-band
inputs.

Power consumption can be further reduced by slowing down
the master clock input to the minimum clock frequency,
F

CLOCK

, specified for the AD1878/AD1879.

APPLICATIONS ISSUES
Recommended Input Structure

The AD1878/AD1879 input structure is fully differential for
improved common-mode rejection properties and increased
dynamic range. Since each input pin sees

3 V swings, each

channel's input signal effectively swings

6 V, i.e., across a

12 V range.

In most cases, a single-ended-to-differential input circuit is
required. Shown in Figure 2 is our recommended circuit, based
on extensive experimentation. Note that to maximize signal
swing, the op amps in this circuit are powered by

12 V or

greater supplies. The AD1878/AD1879 itself requires

5 V

supplies. If

5 V supplies are not already available in your sys-

tem, Figure 3 illustrates our recommended circuit for generat-
ing these supplies.

AD1878/AD1879

REV. 0

RIGHT INPUT

NE5532 OR OP-275

100pF

.1µF

5.76k

100pF

249k

100k

249k

.1µF

.0047 µF

NPO

.01µF

NPO

.01µF
NPO

NE5532 OR

OP-275

VINR

VINR+

VINL+

VINL

REFR

REFL

10µF

.1µF

AD1878/79

LEFT
INPUT

100pF

.1µF

.0047 µF

NPO

.01µF
NPO

NE5532 OR

OP-275

.1µF

.01µF

NPO

10µF

5.62k

5.49k

200

249k

5.62k

100k

5.36k

200

5.62k

249k

5.90k

Figure 2. AD1878/AD1879 Recommended Input Structure

AGND

DGND

0.1µF

22µF

7805

OUT

GND

+5V ANALOG

5V
ANALOG

+5V DIGITAL

+12V < V

< +18V

12V > V

> 18V

0.1µF

22µF

0.1µF

22µF

7905

OUT

GND

0.1µF

10µF

0.1µF

10µF

Figure 3. AD1878/AD1879 Recommended Power Condi-
tioning Circuit (If

5 V Supplies Are Not Already Available)

The trim potentiometers shown in Figure 2 connecting the
minus () inputs of the driving op amps permit trimming out dc
offset, if desired.

Note that the driving op amp feedback resistors are all slightly
different values. These values produce a slight differential gain
imbalance and were derived empirically to minimize second
harmonic distortion on average and produce the best overall
THD without part-by-part trimming. Replacing one of these
feedback resistors in each channel with a trim potentiometer
allows trimming the differential gain imbalance for part-by-part
optimal performance. We have done this in the lab by parallel-
ing 100 k

trim potentiometers around the 5.49 k

and

5.36 k

input feedback resistors for the V

plus (+) signals

that can be found in Figure 2. By trimming gain imbalance, sec-
ond harmonic distortion can always be eliminated. In "Specifi-
cations," a distinction is drawn between trimmed and untrimmed
signal-to (noise + distortion) and trimmed and untrimmed total
harmonic distortion. The untrimmed specifications are tested to

the input structure shown in Figure 2. The trimmed specifica-
tions are based on a part-by-part trim of this differential gain to
eliminate the second harmonic.

The input circuit of Figure 2 could be implemented with a
single pair of operational amplifiers per channel, one inverting
and one noninverting. The recommended architecture shown in
Figure 2 using three inverting op amps per channel provides iso-
lation of the op amp inputs from charge dumped back from the
AD1878/AD1879's input capacitors when these large capacitors
switch. The performance from a two op amp per channel input
structure is not quite as good as the structure recommended,
but it is close and may be adequate in many applications.

Layout and Decoupling Considerations

Obtaining the best possible performance from a state-of-the-art
data converter like the AD1878/AD1879 requires close atten-
tion to board layout. From extensive experimentation, we have
discovered principles that produce typical values of 103 dB dy-
namic range and 98 dB S/(THD+N) in your system. Schematics
of our AD1878/AD1879 Evaluation Board, which implements
these recommendations, are available from Analog Devices.

The principles and their rationales are listed below in descend-
ing order of importance. The first two pertain to bypassing and
are illustrated in Figure 4.

AD1878/ 79

1 AV

1 AGND AGND

10µF

5V

ANALOG

+5V

ANALOG

10µF

0.1µF

+5V

DIGITAL

10µF

0.1µF

+5V

DIGITAL

2 AV

2 DV

DGND DGND DV

5V

ANALOG

+5V

ANALOG

+5V DIGITAL

OSCILLATOR

0.1µF

CLKIN

10µF

Figure 4. AD1878/AD1879 Recommended Bypassing and
Oscillator Circuits

The digital bypassing of the AD1878/AD1879 is the most
critical item on the board layout. There are two pairs of digi-
tal supply pins of the part, each pair on opposite sides (Pins 5
and 6 and Pins 22 and 23). The user should tie a bypass ca-
pacitor set (0.1

F ceramic and 10

F tantalum) on EACH

pair of supply pins as close to the pins as possible. The traces
between these package pins and the capacitors should be as
short and as wide as possible. This will prevent digital supply
current transients from being inductively transmitted to the
inputs of the part.

The analog input bypassing is the second most critical item.
Use 0.01

F NPO ceramic capacitors from each input pin to

the analog ground plane, with a clear ground path from the
bypass capacitor to the AGND pin on the same side of the
package (Pins 10 and 18). The trace between this package
pin and the capacitor should be as short and as wide as pos-
sible. A 0.0047

F NPO ceramic capacitor should be placed

AD1878/AD1879

REV. 0

between each set of input pins (12 to 13, and 17 to 16) to
complete the input bypassing. This input bypassing mini-
mizes the RF transmission and reception capability of the
AD1878/AD1879 inputs.

For best performance, do not use a socket with the AD1878/
AD1879. If you must socket the part, use pin clips to keep
the part flush with the board, thus keeping bypassing as
close to the chip as possible.

The AD1878/AD1879 should be placed on a split ground
plane as illustrated in Figure 5. The digital ground plane
should be placed under the top end of the package and the
analog ground plane should be placed under the bottom end
of the package as shown in Figure 5. The split should be be-
tween Pins 7 and 8 and between Pins 21 and 22. The
ground planes should be tied together at one spot under-
neath the center of the package. This ground plane tech-
nique also minimizes RF transmission and reception.

LRCK

BCK

64/32

DGND

AGND

APD

VINR

VINR+

REFR

WCK

DATA

CLK

DGND

AGND

VINL

VINL+

REFL

RESET

DIGITAL GROUND

PLANE

ANALOG GROUND

PLANE

Figure 5. AD1878/AD1879 Recommended Ground Plane

Each reference pin (14 and 15) should be bypassed with a
resistor and a capacitor. One end of the resistor should be
placed as close to the package pin as possible, and the trace
to it from the reference pin should be as short and as wide as
possible. Keep this trace away from input pin traces! Cou-
pling between input and reference traces will cause second
harmonic distortion. The resistor is used to reduce the high
frequency coupling into the references from the board.

Wherever possible, minimize the capacitive load on digital
outputs of the part. This will reduce the digital spike cur-
rents drawn from the digital supply pins.

How to Extend SNR

A cost-effective method of improving the dynamic range and
SNR of an analog-to-digital conversion system is to use mul-
tiple AD1879 channels in parallel with a common analog input.
(The same technique would work with the AD1878. However,
this would be of little value since using a single AD1879 would

be more effective.) This technique makes use of the fact that the
noise in independent modulator channels is uncorrelated. Thus
every doubling of the number of AD1879 channels used will im-
prove system dynamic range by 3 dB. The digital outputs from
the corresponding decimator channels have to be arithmetically
averaged to obtain the improved results in the correct data for-
mat. A digital processor, either general-purpose or DSP, can
easily perform the averaging operation.

Shown below in Figure 6 is a circuit for obtaining a 3 dB im-
provement in dynamic range by using both channels of a single
AD1879 with a mono input. The minus () output from the in-
put buffer is sent to both right and left minus AD1879 inputs;
the plus (+) output from the input buffer is sent to both right
and left plus AD1879 inputs. A stereo implementation would
require using two AD1879s and using the full recommended in-
put structure shown above in Figure 2. Note that a single digital
processor would likely be able to handle the averaging require-
ments for both left and right channels.

PIN 1

0.580 (14.73)

0.485 (12.32)

2
8

0.625 (15.87)
0.600 (15.24)

0.015 (0.381)

0.008 (0.204)

0.195 (4.95)
0.125 (3.18)

0.250

(6.35)

MAX

0.022 (0.558)
0.014 (0.356)

0.100

(2.54)

BSC

0.200 (5.05)
0.125 (3.18)

0.070 (1.77)

MAX

0.060 (1.52)
0.015 (0.38)

0.150
(3.81)
MIN

SEATING
PLANE

1.565 (39.70)
1.380 (35.10)

Figure 6. Increasing Dynamic Range by Using Two
AD1879 Channels

DIGITAL INTERFACE
Modes of Operation

The AD1878/AD1879's flexible serial output port produces
data in twos-complement, MSB-first format. Output signals are
to TTL/CMOS logic levels. The port is configured by pin selec-
tions. The AD1879 can operate in either master or slave modes.
Each 16-/18-bit output word of a stereo pair can be formatted
within a 32-bit field as right-justified, as I

S-compatible, or at

user-selected positions. The two 32-bit fields constitute a 64-bit
frame (64-bit mode). The output can also be truncated to 16
bits and formatted in a 16-bit field with two 16-bit fields in a
32-bit frame (32-bit mode).

The various mode options are pin-programmed with the S0
Mode Select Pin (3), the S1 Mode Select Pin (25), and the
64/32 Bit Rate Select Pin (4). The function of these pins is
summarized:

Serial Port Operation Mode

64/32

64-Bit Master Mode--Word Clock Output

64-Bit Master Mode--Word Clock Input

64-Bit Slave Mode

Reserved

32-Bit Master Mode--Word Clock Out HI

32-Bit Master Mode--Word Clock Ignored

32-Bit Slave Mode

Reserved

Serial Port Data Timing Sequences

In the "master modes," the bit clock (BCK) and left/right clock
(LRCK) are always outputs, generated internally in the AD1878/
AD1879 from the master clock (CLOCK) input. The word
clock (WCK) may either be an internally generated output or a
user-supplied input, depending on the pin-programmed mode
selected.

AD1878/AD1879

REV. 0

In the "slave modes," the bit clock (BCK), the word clock
(WCK), and the left/right clock (LRCK) are user-supplied in-
puts. Note that, for performance reasons, the AD1878/AD1879
does not support asynchronous operation; these clocks must be
externally derived from the master clock (CLOCK). The func-
tional sequence of the signals in the slave modes is identical to
the master modes with word clock input, and they share the
same sequence timing diagrams.

In 64-Bit Master Mode with Word Clock Output, the 16-/18-bit
words are right-justified in 32-bit fields as shown in Figures 7
and 8. The WCK output goes HI approximately with the falling
edge of the BCK output, indicating that the MSB on DATA will
be externally valid at the next BCK rising edge. The LRCK out-
put discriminates the left from the right output fields.

In 64-bit frame modes with word clock (WCK) is an input, the
16-/18-bit words can be placed in user-defined locations within
32-bit fields. This is true in both master and slave modes. The

options are illustrated in Figures 9, 10, 11, and 12. For all op-
tions, the first occurrence in a 32-bit field when the word clock
(WCK) is HI on a bit clock (BCK) falling edge will cause the
beginning of data transmission. The MSB on DATA will be
valid at the next BCK rising edge. Again, the LRCK output dis-
criminates the left from the right output fields.

Figure 9 illustrates the general case for 64-bit frame modes with
word clock input where the MSB is valid on the rising edge of
the Nth bit clock (BCK). Figures 10 and 11 illustrate the limits.
If WCK is still LO at the falling edge of the 14th bit clock (BCK)
for the AD1879 or 16th bit clock (BCK) for the AD1878, then the
MSB of the current word will be output anyway, valid at the ris-
ing edge of the 15th bit clock (BCK) in the field for the AD1879,
17th for the AD1878. This limit insures that all 16/18 bits will
be output within the current field. The effect is to right-justify
the data.

MSB

MSB1 MSB2 MSB3

LEFT DATA

ZEROS

LSB3

LSB

MSB

MSB1 MSB2 MSB3

RIGHT DATA

ZEROS

LSB2 LSB1

LSB3

LSB

LSB2 LSB1

BCK

OUTPUT

WCK

OUTPUT

LRCK

OUTPUT

PREVIOUS DATA

DATA

OUTPUT

Figure 7. AD1879 64-Bit Output Timing with WCK as Output (Master Mode Only)

BCK

OUTPUT

WCK

OUTPUT

LRCK

OUTPUT

MSB MSB1

LEFT DATA

ZEROS

LSB3

LSB

PREVIOUS DATA

RIGHT DATA

ZEROS

DATA

OUTPUT

LSB

LSB1

LSB2

MSB

MSB1

LSB3

LSB

LSB1

LSB2

Figure 8. AD1878 64-Bit Frame Output Timing with WCK as Output (Master Mode Only)

LSB-2

LSB

BCK I/O

N1

N+1

WCK INPUT

AD1879

DATA OUTPUT

MSB1

ZEROS

LSB3

LRCK I/O

N+14

N+17

N+15 N+16

LSB1

N1

N+1

MSB

MSB1

ZEROS

LSB

LSB3

LSB-2

LSB1

AD1878

DATA OUTPUT

MSB

MSB1

ZEROS

LSB1

LSB

MSB

MSB1

ZEROS

LSB1

LSB

N+14

N+17

N+15 N+16

RIGHT DATA

LEFT DATA

MSB

Figure 9. AD1878/AD1879 64-Bit Frame Output Timing with WCK as Input: WCK Transitions HI Before 16th BCK
(AD1878)/14th BCK (AD1879) (Master Mode or Slave Mode)

AD1878/AD1879

REV. 0

MSB

WCK INPUT

MSB1 MSB2 MSB3

ZEROS

LSB1

LSB

ZEROS

LSB

LSB1

BCK I/O

LRCK I/O

AD1878

DATA OUTPUT

MSB

MSB1 MSB2 MSB3

LEFT DATA

PREVIOUS DATA

RIGHT DATA

Figure 10. AD1878 64-Bit Frame Output Timing with WCK as Input: WCK Held LO Until 16th BCK
(Master Mode or Slave Mode)

WCK INPUT

MSB

MSB1 MSB2 MSB3 MSB4 MSB5

ZEROS

LSB1

LSB

PREVIOUS DATA

MSB

MSB1 MSB2 MSB3 MSB4 MSB5

ZEROS

LSB

LSB1

BCK I/O

LRCK I/O

AD1879

DATA OUTPUT

LEFT DATA

RIGHT DATA

Figure 11. AD1879 64-Bit Frame Output Timing with WCK as Input: WCK Held LO Until 14th BCK
(Master Mode or Slave Mode)

LSB-2

WCK INPUT

ZEROS

BCK I/O

LRCK I/O

RIGHT DATA

AD1879

DATA OUTPUT

MSB

MSB1

ZEROS

LSB3

LSB1

LSB

AD1878

DATA OUTPUT

MSB

MSB1

ZEROS

LSB1

LSB

ZEROS

MSB

MSB1

ZEROS

LSB3

LSB1

LSB

MSB

MSB1

ZEROS

LSB1

LSB

ZEROS

RIGHT DATA

LEFT DATA

Figure 12. AD1878/AD1879 64-Bit Output Frame Timing with WCK as Input: WCK Hl During 1st BCK
(Master Mode or Slave Mode)

LEFT DATA

MSB

MSB1 MSB2 MSB3 MSB4 MSB5

LSB3

BCK I/O

LRCK I/O

RIGHT DATA

MSB

MSB1 MSB2 MSB3 MSB4 MSB5

LSB2

LSB3 LSB2

AD1879

DATA OUTPUT

AD1878

DATA OUTPUT

LEFT DATA

MSB

MSB1 MSB2 MSB3 MSB4 MSB5

LSB-1

RIGHT DATA

MSB

MSB1 MSB2 MSB3 MSB4 MSB5

LSB

LSB-1

LSB

Figure 13. AD1878/AD1879 32-Bit Output Frame Timing (Master Mode or Slave Mode)

At the other limit, if the word clock (WCK) is HI during the first
bit clock (BCK) of the field, then the MSB of the output word
will be valid on the rising edge of the 2nd bit clock (BCK) as
shown in Figure 12. The effect is to delay the MSB for one bit
clock cycle into the field, making the output data compatible at
the data format level with the I

S data format.

In 64-bit frame modes with word clock (WCK) as an input, the
relative placement of the word clock (WCK) input can vary
from 32-bit field to 32-bit field, even within the same 64-bit
frame. For example, within a single 64-bit frame the left word
could be right-justified (by keeping WCK LO) and the right
word could be in an I

S-compatible data format (by having

WCK HI at the beginning of the second field).

AD1878/AD1879

REV. 0

delayed from a master clock input (CLOCK) rising edge by
t

DLYCK

as shown in Figure 15. The MSB of the DATA output

will be delayed from a falling edge of master clock (CLOCK) by
t

DLYD,MSB

. Subsequent bits of the DATA output in contrast will

be delayed from a rising edge of master clock (CLOCK) by
t

DLYD

. (The MSB is valid one-half CLOCK period less than the

subsequent bits.)

For master modes with word clock (WCK) inputs, bit clock
(BCK) and left/ right clock (LRCK) will be delayed from a
master clock input (CLOCK) rising edge by t

DLYCK

as shown in

Figure 16, the same delay as with word clock output modes.
The word clock (WCK) input, however, now has a setup time
requirement, t

WSET

, to the rising edge of master clock (CLOCK

at "W") and a corresponding hold time, t

WHLD

, from the rising

of the third rising edge of CLOCK (W+3) after the setup edge.
See Figure 16. As in the Master Mode--Word Clock Output
case, the MSB of the DATA output will be delayed from a fall-
ing edge of master clock (CLOCK) by t

DLYD,MSB

. Subsequent

bits of the DATA output in contrast will be delayed from a ris-
ing edge of master clock (CLOCK) by t

DLYD

For slave modes, bit clock (BCK) and left/right clock (LRCK)
will be inputs with setup time, t

SET

, and hold time t

HLD

requirements to the falling edges of CLOCK as shown in Fig-
ure 17. Note that both edges of BCK and of LRCK have setup
and hold time requirements. Note also that LRCK is setup to
the falling edge of the "L" CLOCK, coincident with the CLOCK
edge to which a falling edge of BCK is setup (B+3). LRCK's
hold time requirements are relative to the falling edge of the
"L + 31" CLOCK edge.

Also available with the AD1878/AD1879 is a 32-bit frame mode
where the 1879's 18-bit output is truncated to 16-bit words and
for both parts the output packed "tightly" into two 16-bit fields
in the 32-bit frame as shown in Figure 13. Note that the bit
clock (BCK) and data transmission (DATA) are operating at
one-half the rate as they would in the 64-bit frame modes. The
distinction between master and slave modes still holds in the
32-bit frame modes, though the word clock (WCK) becomes ir-
relevant. If "32-Bit Master Mode With Word Clock Out HI" is
selected, the word clock (WCK) will stay in a constant HI state.
If "32-Bit Master Mode With Word Clock Ignored" is selected,
the word clock pin (WCK) will be three-stated and any input to
it is ignored as meaningless. (However, such an input should be
tied off to HI or LO and not left to float.)

In both 32-bit master modes, the left/right clock (LRCK) will be
an output, indicating the difference between the left word/field
and right word/field. In 32-Bit Slave Mode, the left/right clock
(LRCK) is an input.

Timing Parameters

The AD1878/AD1879 uses its master clock, CLOCK to resyn-
chronize all inputs and outputs. The discussion above presumed
that most timing parameters are relative to the bit clock, BCK.
This is approximately true and provides an accurate model of
the sequence of timing events. However, to be more precise, we
have to specify all setup and hold times relative to CLOCK.
These are illustrated in Figures 15, 16, and 17.

For master modes with word clock (WCK) output, bit clock
(BCK), left/right clock (LRCK), and word clock (WCK) will be

RSET

CLOCK INPUT

RESET

RHLD

RPLS

MIN 4 CLKS

FOR SYNCH

MIN 1 CLK

MAX 2 CLKS

FOR SYNCH

MIN 4 CLKS

FOR SYNCH

126 127 128

LRCK OUTPUT

BCK OUTPUT

Figure 14. AD1878/AD1879 RESET Clock Timing for Synchronizing Master Mode WCK Output

DATA OUTPUT

BCK OUTPUT (64·F

)

CLOCK INPUT

LRCK & WCK OUTPUTS

DLYD,MSB

PREVIOUS

NEW

MSB

MSB2

MSB1

DLYD

DLYCK

ZEROS

Figure 15. AD1878/AD1879 Master Mode Clock Timing: WCK Output

AD1878/AD1879

REV. 0

DATA OUTPUT

BCK OUTPUT (64·F

)

CLOCK INPUT

LRCK OUTPUT

WCK INPUT

PREVIOUS

NEW

DLYCK

WSET

WHLD

DLYD,MSB

MSB

MSB2

MSB1

DLYD

DLYCK

ZEROS

W+1 W+2 W+3

Figure 16. AD1878/AD1879 Master Mode Clock Timing: WCK Input

DATA OUTPUT

BCK INPUT (64·F

)

CLOCK INPUT

LRCK INPUT

WCK INPUT

HLD

SET

L+1

W+1 W+2 W+3

WSET

WHLD

DLYD,MSB

MSB

MSB2

MSB1

DLYD

SET

HLD

B+1 B+2

B+3

L+30 L+31

HLD

ZEROS

Figure 17. AD1878/AD1879 Slave Mode Timing

For slave modes, the word clock (WCK) input has the same
setup time requirement, t

WSET

, to the rising edge of master

clock (CLOCK at "W" ) as in Figure 16 and a corresponding
hold time, t

WHLD

, from the rising edge of CLOCK (W+3) after

the setup edge. The MSB of the DATA output will be delayed
from a falling edge of master clock (CLOCK) by t

DLYD,MSB

Subsequent bits of the DATA output in contrast will be delayed
from a rising edge of master clock (CLOCK) by t

DLYD

Synchronizing Multiple AD1878/AD1879s

Multiple AD1878/AD1879s can be synchronized either by
making all AD1878/AD1879s serial port slaves or by making
one AD1879 the serial port master and all other AD1879s
slaves. These two options are illustrated in Figure 18.

As a third alternative, it is possible to synchronize multiple mas-
ters all in Master Mode--Word Clock Output mode. See the
"Reset" discussion above in the "Operating Features" section
for timing considerations.

AD1878/AD1879 to DSP56001 Interface

The 18-bit AD1878/AD1879 can be interfaced quite simply to
the DSP56001 Digital Signal Processor. Figure 19 illustrates
one method of connection. In this implementation, the AD1878/
AD1879 is configured to operate in 64-Bit Master Mode With

Word Clock Output. Thus, the AD1878/AD1879 is the master
of the serial interface. The AD1878/AD1879 operates indepen-
dently from the DS

Ps clock. The DSP56001 serial port is

configured to operate in synchronous mode with the AD1878/
AD1879 connected to its synchronous serial interface (SSI) port.

CLOCK

SOURCE

AD1879

MASTER MODE

CLK

DATA

BCK

WCK

LRCK

AD1879

SLAVE MODE

CLK

DATA

BCK

WCK

LRCK

AD1879

SLAVE MODE

CLK

DATA

BCK

WCK

LRCK

CLOCK

SOURCE

AD1879

SLAVE MODE

CLK

DATA

BCK

WCK

LRCK

AD1879

SLAVE MODE

CLK

DATA

BCK

WCK

LRCK

AD1879

SLAVE MODE

CLK

DATA

BCK

WCK

LRCK

Figure 18. Synchronizing Multiple AD1878/AD1879s

AD1878/AD1879

REV. 0

DATA

BCK

WCK

LRCK

AD1879

SRD

SCK

SC2

SC1

DSP56001

Figure 19. AD1879 to DSP56001 Interface

To configure the DSP56001 for proper operation, the CRA
register must he programmed for a 24-bit receive data register
(RX). The CRB register must be programmed with the follow-
ing conditions: receiver enabled, normal mode, continuous
clock, word length frame synch, MSB first, SCK an input, SC1
an input and SC2 an input. The PCC register must be pro-
grammed to set the SCK, SC1, SC2, and SRD pins of Port C
to operate as a serial interface rather than in general-purpose
parallel I/O mode.

When SSI detects the rising edge of the AD1878/AD1879's
word clock (WCK), the next 24-bits on the AD1878/AD1879's
DATA pin will be clocked into the DSP56001's SSI receive
shift register on the falling edges of the inverted bit-clock
(BCK) signal. This data is then transferred to the RX register.
The 16-/18-bit word from the AD1879 will be located in Bits 8
through 23/21 of the RX register. Bits 0 through 7 will be
zero-filled. The user may poll Bit 7 (RDF) of the SSI status
register (SSISR) to detect when the data has been transferred
to RX. Alternatively, the RIE bit can be set, allowing an inter-
rupt to occur when the data has been transferred.

To differentiate left and right data, the SC1 pin of the SSI is an
input and is connected to the LRCK of the AD1878/AD1879.
After a data word is transferred to the RX register, the software
reads the IF1 bit in the SSISR, which contains the left/right in-
formation. In order to use the SC1 pin as indicated, the SSI
must operate in synchronous mode. An DSP56001 assembly
code fragment for this approach (with polling) is shown in
Table I.

Table I. DSP56001 Assembly Code for AD1878/AD1879 Data
Transfer

poll jclr

#7,X:$FFEE,poll

:loop until RX reg. has data

movep

X:$FFEF,al:

:transfer ADC to al register

jset

#I:X:$FFEE,left

:if LRCK=1, save left else

move

a1,X:$C000

:store right channel

jmp

poll

:wait for next input

left move

a1,Y:$C000

:store left channel

jump poll

If the SSI is set up for asynchronous operation, the SC0 and
SC1 pins are unavailable for left/right detection. If asynchro-
nous operation is essential, left/right information can be ob-
tained by synchronizing the AD1878/AD1879 with a software
reset. Coming out of reset, the AD1878/AD1879 will transmit
left channel data first. A flag maintained in software can main-
tain the synchronization.

AD1878/AD1879 PERFORMANCE GRAPHS

140

24k

80

120

100

20

60

40

22k

20k

18k

16k

14k

12k

10k

FREQUENCY Hz

dBFS

Figure 20. AD1879 S/(THD+N)--1 kHz Tone at 0.5 dBFS
(4k-Point FFT)

140

24k

80

120

100

20

60

40

22k

20k

18k

16k

14k

12k

10k

FREQUENCY Hz

dBFS

Figure 21. AD1879 S/(THD+N)--1 kHz Tone at 10 dBFS
(4k-Point FFT)

140

24k

80

120

100

20

60

40

22k

20k

18k

16k

14k

12k

10k

FREQUENCY Hz

dBFS

Figure 22. AD1879 S/(THD+N)--1 kHz Tone at 60 dBFS
(4k-Point FFT)

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: AD1878

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: AD1878