FUNCTIONAL BLOCK DIAGRAM
1
2
3
4
5
6
7
8
9
LATCH
DAC
SERIAL
INPUT
REGISTER
CONTROL
LOGIC
AD1851/
AD1861
DGND
NC
CLK
LE
DATA
NC = NO CONNECT
TRIM
MSB ADJ
I
OUT
AGND
SJ
R
F
V
OUT
10
11
12
13
14
15
16
NC
+V
S
V
S
+V
L
I
OUT
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
16-Bit/18-Bit, 16 F
S
PCM Audio DACs
AD1851/AD1861
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
FEATURES
110 dB SNR
Fast Settling Permits 16 Oversampling
3 V Output
Optional Trim Allows Super-Linear Performance
5 V Operation
16-Pin Plastic DIP and SOIC Packages
Pin-Compatible with AD1856 & AD1860 Audio DACs
2s Complement, Serial Input
APPLICATIONS
High-End Compact Disc Players
Digital Audio Amplifiers
DAT Recorders and Players
Synthesizers and Keyboards
PRODUCT DESCRIPTION
The AD1851/AD1861 is a monolithic PCM audio DAC. The
AD1851 is a 16-bit device, while the AD1861 is an 18-bit de-
vice. Each device provides a voltage output amplifier, DAC,
serial-to-parallel register and voltage reference. The digital por-
tion of the AD1851/AD1861 is fabricated with CMOS logic
elements that are provided by Analog Devices' 2
m ABCMOS
process. The analog portion of the AD1851/AD1861 is fabri-
cated with bipolar and MOS devices as well as thin-film
resistors.
This combination of circuit elements, as well as careful design
and layout techniques, results in high performance audio play-
back. Laser-trimming of the linearity error affords low total har-
monic distortion. An optional linearity trim pin is provided to
allow residual differential linearity error at midscale to be elimi-
nated. This feature is particularly valuable for low distortion
reproductions of low amplitude signals. Output glitch is also
small, contributing to the overall high level of performance. The
output amplifier achieves fast settling and high slew rates, pro-
viding a full
3 V signal at load currents up to 8 mA. When
used in current output mode, the AD1851/AD1861 provides a
1 mA output signal. The output amplifier is short circuit
protected and can withstand indefinite shorts to ground.
The serial input interface consists of the clock, data and latch
enable pins. The serial 2s complement data word is clocked into
the DAC, MSB first, by the external clock. The latch enable
signal transfers the input word from the internal serial input
register to the parallel DAC input register. The AD1851 input
clock can support a 12.5 MHz data rate, while the AD1861 in-
put clock can support a 13.5 MHz data rate. This serial input
port is compatible with second generation digital filter chips
used in consumer audio products. These filters operate at over-
sampling rates of 2 , 4 , 8 and 16 sampling frequencies.
The critical specifications of THD+N and signal-to-noise ratio
are 100% tested for all devices.
The AD1851/AD1861 operates with
5 V power supplies, mak-
ing it suitable for home use markets. The digital supply, V
L
, can
be separated from the analog supplies, V
S
and V
S
, for reduced
digital crosstalk. Separate analog and digital ground pins are
also provided. Power dissipation is 100 mW typical.
The AD1851/AD1861 is available in either a 16-pin plastic DIP
or a 16-pin plastic SOIC package. Both packages incorporate
the industry standard pinout found on the AD1856 and
AD1860 PCM audio DACs. As a result, the AD1851/AD1861
is a drop-in replacement for designs where
5 V supplies have
been used with the AD1856/AD1860. Operation is guaranteed
over the temperature range of 25
C to +70
C and over the
voltage supply range of
4.75 V to
5.25 V.
PRODUCT HIGHLIGHTS
l. AD1851 16-bit resolution provides 96 dB dynamic range.
AD1861 18-bit resolution provides 108 dB dynamic range.
2. No external components are required.
3. Operates with
5 V supplies.
4. Space saving 16-pin SOIC and plastic DIP packages.
5. 100 mW power dissipation.
6. High input clock data rates and 1.5
s settling time permits
2 , 4 , 8 and 16 oversampling.
7.
3 V or
1 mA output capability.
8. THD + Noise and SNR are 100% tested.
9. Pin-compatible with AD1856 & AD1860 PCM audio DACs.
REV. A
2
AD1851/AD1861SPECIFICATIONS
(T
A
@ +25 C and 5 V supplies, unless otherwise noted)
NC = NO CONNECT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
16-BIT
LATCH
16-BIT
DAC
SERIAL
INPUT
REGISTER
CONTROL
LOGIC
AD1851
DGND
NC
CLK
LE
DATA
TRIM
MSB ADJ
AGND
SJ
NC
V
S
+V
L
+V
S
I
OUT
R
F
V
OUT
I
OUT
AD1851 Functional Block Diagram
NC = NO CONNECT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
16-BIT
LATCH
16-BIT
DAC
SERIAL
INPUT
REGISTER
CONTROL
LOGIC
AD1851
DGND
NC
CLK
LE
DATA
TRIM
MSB ADJ
AGND
SJ
NC
V
S
+V
L
+V
S
I
OUT
R
F
V
OUT
I
OUT
AD1861 Functional Block Diagram
Min
Typ
Max
Units
DIGITAL INPUTS
V
IH
2.0
+V
L
V
V
IL
0.8
V
I
IH
, V
IH
= V
L
1.0
A
I
IL
, V
IL
= 0.4
10
A
ACCURACY
Gain Error
1
%
Midscale Output Voltage
10
mV
DRIFT (0
C to +70
C)
Total Drift
25
ppm of FSR/
C
Bipolar Zero Drift
4
ppm of FSR/
C
SETTLING TIME (To
0.0015% of FSR)
Voltage Output
6 V Step
1.5
s
1 LSB Step
1.0
s
Slew Rate
9
V/
s
Current Output
1 mA Step 10
to 100
Load
350
ns
1 k
Load
350
ns
OUTPUT
Voltage Output Configuration
Bipolar Range
2.88
3.0
3.12
V
Output Current
8
mA
Output Impedance
0.1
Short Circuit Duration
Indefinite to Common
Current Output Configuration
Bipolar Range (
30%)
1.0
mA
Output Impedance (
30%)
1.7
k
POWER SUPPLY
Voltage
+V
L
and +V
S
4.75
5.25
V
V
S
5.25
4.75
V
TEMPERATURE RANGE
Specification
0
+25
+70
C
Operation
25
+70
C
Storage
60
+100
C
WARM-UP TIME
1
min
Specifications subject to change without notice.
REV. A
3
AD1851
Min
Typ
Max
Units
RESOLUTION
16
Bits
TOTAL HARMONIC DISTORTION + NOISE
0 dB, 990.5 Hz
AD1851N-J, R-J
0.003
0.004
%
AD1851N, R
0.004
0.008
%
20 dB, 990.5 Hz
AD1851N-J, R-J
0.009
0.016
%
AD1851N, R
0.009
0.040
%
60 dB, 990.5 Hz
AD1851N-J, R-J
0.9
1.6
%
AD1851N, R
0.9
4.0
%
D-RANGE* (With A-Weight Filter)
60 dB, 990.5 Hz AD1851N, R
88
dB
AD1851N-J, R-J
96
dB
SIGNAL-TO-NOISE RATIO
107
110
dB
MAXIMUM CLOCK INPUT FREQUENCY
12.5
MHz
ACCURACY
Differential Linearity Error
0.001
% of FSR
MONOTONICITY
14
Bits
POWER SUPPLY
Current
+I
10.0
13.0
mA
I
10.0
15.0
mA
Power Dissipation
100
mW
AD1861
Min
Typ
Max
Units
RESOLUTION
18
Bits
TOTAL HARMONIC DISTORTION + NOISE
0 dB, 990.5 Hz
AD1861N-J, R-J
0.003
0.004
%
AD1861N, R
0.004
0.008
%
20 dB, 990.5 Hz
AD1861N-J, R-J
0.009
0.016
%
AD1861N, R
0.009
0.040
%
60 dB, 990.5 Hz
AD1861N-J, R-J
0.9
1.6
%
AD1861N, R
0.9
4.0
%
D-RANGE* (With A-Weight Filter)
60 dB, 990.5 Hz AD1861N, R
88
dB
AD1861N-J, R-J
96
dB
SIGNAL-TO-NOISE RATIO
107
110
dB
MAXIMUM CLOCK INPUT FREQUENCY
13.5
MHz
ACCURACY
Differential Linearity Error
0.001
% of FSR
MONOTONICITY
15
Bits
POWER SUPPLY
Current
+I
10.0
13.0
mA
I
10.0
15.0
mA
Power Dissipation
100
mW
*Tested in accordance with EIAJ Test Standard CP-307.
Specifications subject to change without notice.
AD1851/AD1861
AD1851/AD1861
REV. A
4
ABSOLUTE MAXIMUM RATINGS*
V
L
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 6.50 V
V
S
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 6.50 V
V
S
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . 6.50 V to 0 V
Digital Inputs to DGND . . . . . . . . . . . . . . . . . . . 0.3 V to V
L
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0.3 V
Short Circuit . . . . . . . . . . . . . . . . . Indefinite Short to Ground
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300
C, 10 sec
Storage Temperature . . . . . . . . . . . . . . . . . . 60
C to +100
C
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
PIN DESCRIPTIONS
1
V
S
Analog Negative Power Supply
2
DGND
Logic Ground
3
V
L
Logic Positive Power Supply
4
NC
No Connection
5
CLK
Clock Input
6
LE
Latch Enable Input
7
DATA
Serial Data Input
8
NC
No Internal Connection*
9
V
OUT
Voltage Output
10
R
F
Feedback Resistor
11
SJ
Summing Junction
12
AGND
Analog Ground
13
I
OUT
Current Output
14
MSB ADJ
MSB Adjustment Terminal
15
TRIM
MSB Trimming Potentiometer Terminal
16
V
S
Analog Positive Power Supply
*Pin 8 has no internal connection; -V
L
from AD1856 or AD1860 socket can be
safely applied.
ORDERING GUIDE
Package
Model
Resolution
THD + N
Option*
AD1851N
16 Bits
0.008%
N-16
AD1851N-J
16 Bits
0.004%
N-16
AD1851R
16 Bits
0.008%
R-16
AD1851R-J
16 Bits
0.004%
R-16
AD1861N
18 Bits
0.008%
N-16
AD1861N-J
18 Bits
0.004%
N-16
AD1861R
18 Bits
0.008%
R-16
AD1861R-J
18 Bits
0.004%
R-16
*N = Plastic DIP Package; R = Small Outline (SOIC) Package.
CAUTION
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected;
however, permanent damage may occur on unconnected devices subject to high energy electro-
static fields. Unused devices must be stored in conductive foam or shunts. The protective foam
should be discharged to the destination socket before devices are inserted .
WARNING!
ESD SENSITIVE DEVICE
Typical Performance
175
150
125
100
75
50
25
2
4
6
8
10
12
14
CLOCK FREQUENCY MHz
PD mW
Power Dissipation vs. Clock Frequency
THD+N %
10
1
0.1
0.01
0.001
30 20 10
0
10
20
30
40
50
60
70
80
90
TEMPERATURE
C
60dB
20dB
0dB
THD vs. Temperature
AD1851/AD1861
REV. A
5
TOTAL HARMONIC DISTORTION
Total harmonic distortion plus noise (THD+N) is defined as
the ratio of the square root of the sum of the squares of the val-
ues of the first 19 harmonics and noise to the value of the funda-
mental input frequency. It is usually expressed in percent (%).
THD+N is a measure of the magnitude and distribution of lin-
earity error, differential linearity error, quantization error and
noise. The distribution of these errors may be different, depend-
ing on the amplitude of the output signal. Therefore, to be most
useful, THD+N should be specified for both large (0 dB) and
small signal amplitudes (20 dB and 60 dB).
The THD+N figure of an audio DAC represents the amount of
undesirable signal produced during reconstruction and playback
of an audio waveform. This specification, therefore, provides a
direct method to classify and choose an audio DAC for a
desired level of performance.
SETTLING TIME
Settling time is the time required for the output of the DAC to
reach and remain within a specified error band about its final
value, measured from the digital input transition. It is a primary
measure of dynamic performance.
MIDSCALE ERROR
Midscale error, or bipolar zero error, is the deviation of the ac-
tual analog output from the ideal output (0 V) when the 2s
complement input code representing half scale is loaded in the
input register.
D-RANGE DISTORTION
D-range distortion is equal to the value of the total harmonic
distortion + noise (THD+N) plus 60 dB when a signal level of
60 dB below full scale is reproduced. D-range is tested with a
1 kHz input sine wave. This is measured with a standard A-
weight filter as specified by EIAJ Standard CP-307.
SIGNAL-TO-NOISE RATIO
The signal-to-noise ratio (SNR) is defined as the ratio of the
amplitude of the output when a full-scale output is present to
the amplitude of the output with no signal present. This is mea-
sured with a standard A-weight filter as specified by EIAJ
Standard CP-307.
REFERENCE
I
OUT
DAC
R
F
AUDIO
OUTPUT
INPUT LATCH
DATA
LE
CLOCK
SERIAL-TO-PARALLEL
CONVERSION
Figure 1. AD1851/AD1861 Functional Block Diagram
FUNCTIONAL DESCRIPTION
The AD1851/AD1861 is a complete monolithic PCM audio
DAC. No additional external components are required for op-
eration. As shown in Figure 1 above, each chip contains a volt-
age reference, an output amplifier, a DAC, an input latch and a
parallel input register.
The voltage reference consists of a bandgap circuit and buffer
amplifier. This combination of elements produces a reference
voltage that is unaffected by changes in temperature and age.
The DAC output voltage, which is derived from the reference
voltage, is also unaffected by these environmental changes.
The output amplifier uses both MOS and bipolar devices to
produce low offset, high slew rate and optimum settling time.
When combined with the on-chip feedback resistor, the output
op amp converts the output current of the AD1851/AD1861 to
a voltage output.
The DAC uses a combination of segmented decoder and R-2R
architecture to achieve consistent linearity and differential lin-
earity. The resistors which form the ladder structure are fabri-
cated with silicon chromium thin film. Laser-trimming of these
resistors further reduces linearity error, resulting in low output
distortion.
The input register and serial-to-parallel converter are fabricated
with CMOS logic gates. These gates allow the achievement of
fast switching speeds and low power consumption. This contrib-
utes to the overall low power dissipation of the AD1851/
AD1861.
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